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參數(shù)資料
型號(hào)： AD7661ASTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT W/REF 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 25mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)偽差分，單極
配用： EVAL-AD7661CBZ-ND - BOARD EVALUATION FOR AD7661
AD7661
Rev. 0 | Page 16 of 28
CIRCUIT INFORMATION
SWA
COMP
SWB
IN
REF
REFGND
LSB
MSB
32,768C
INGND
16,384C
4C
2C
C
65,536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
03033-0-020
CNVST
Figure 24. ADC Simplified Schematic
The AD7661 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC). The AD7661 is
capable of converting 100,000 samples per second (100 kSPS)
and allows power savings between conversions.
The AD7661 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7661 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in
either a 48-lead LQFP or a 48-lead LFCSP that saves space and
allows flexible configurations as either a serial or parallel inter-
face. The AD7661 is pin-to-pin compatible with PulSAR ADCs
and is an upgrade of the AD7651.
CONVERTER OPERATION
The AD7661 is a successive-approximation ADC based on a
charge redistribution DAC. Figure 24 shows a simplified sche-
matic of the ADC. The capacitive DAC consists of an array of
16 binary weighted capacitors and an additional LSB capacitor.
The comparator’s negative input is connected to a dummy
capacitor of the same value as the capacitive DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SWA. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal on IN. Similarly, the
dummy capacitor acquires the analog signal on INGND.
When CNVST goes LOW, a conversion phase is initiated. When
the conversion phase begins, SWA and SWB are opened. The
capacitor array and dummy capacitor are then disconnected
from the inputs and connected to REFGND. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between REFGND and REF,
the comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4, …VREF/65536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition.
After this process is completed, the control logic generates the
ADC output code and brings the BUSY output LOW.
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