- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1981 > AD7485BSTZ (Analog Devices Inc)IC ADC 14BIT SAR 1MSPS 48-LQFP PDF資料下載
參數(shù)資料
| 型號： | AD7485BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SAR 1MSPS 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
REV.
AD7485
–11–
SERIAL INTERFACE
The AD7485 has two serial interface modes, selected by the state
of the SMODE pin. In both these modes, the MCLK pin must be
supplied with a clock signal of between 10 kHz and 25 MHz. This
MCLK signal controls the internal conversion process and is also
used to derive the SCO signal. As the AD7485 uses an algorithmic
successive-approximation technique, 24 MCLK cycles are
required to complete a conversion. Due to the error-correcting
operation of this ADC, all bit trials must be completed before the
conversion result is calculated. This results in a single sample
delay in the result that is clocked out.
In Serial Mode 1 (Figure 13), the
CONVST pin is used to
initiate the conversion and also frame the serial data. When
CONVST is brought low, the SDO line is taken out of three-
state, the overrange bit will be clocked out on the next rising
edge of SCO followed by the 14 data bits (MSB first) and a
trailing zero.
CONVST must remain low for 22 SCO pulses to
allow all the data to be clocked out and the conversion in
progress to be completed. When
CONVST returns to a logic
high, the SDO line returns to three-state.
TFS should be tied to
ground in this mode.
In Serial Mode 2 (Figure 14), the
CONVST pin is used to
initiate the conversion, but the
TFS signal is used to frame the
serial data. The
CONVST signal can idle high or low in this
mode. Idling high, the
CONVST pulsewidth must be between
10 ns and two MCLK periods. Idling low, the
CONVST
pulsewidth must be at least 10 ns.
TFS must remain low for a
minimum of 22 SCO cycles in this mode but can also be tied
permanently low. If
TFS is tied low, the SDO line will always
be driven.
The relationship between the MCLK and SCO signals is shown
in Figure 15.
Figure 11 shows a typical connection diagram for the AD7485.
In this case, the MCLK signal is provided by a 25 MHz crystal
oscillator module. It could also be provided by the second serial
port of a DSP (e.g., ADSP-2189M) if one were available.
In Figure 11 the VDRIVE pin is tied to DVDD, which results in logic
output levels being either 0 V or DVDD. The voltage applied to
VDRIVE controls the voltage value of the output logic signals. For
example, if DVDD is supplied by a 5 V supply and VDRIVE by a 3 V
supply, the logic output levels would be either 0 V or 3 V. This
feature allows the AD7485 to interface to 3 V devices while still
enabling the A/D to process signals at 5 V supply.
The maximum slew rate at the input of the ADC should be
limited to 500 V/
s while the conversion is taking place. This
will prevent corruption of the current conversion. In any multi-
plexed application, the channel switching should occur as early
as possible after the first MCLK period.
C/ P
RESET
SMODE
NAP
STBY
CONVST
TFS
SCO
SDO
CBIAS
REFSEL
REFIN
REFOUT
VIN
AD7485
ADM809
VDRIVE DVDD AVDD
0.1 F
DIGITAL
SUPPLY
4.75V–5.25V
10 F
1nF
+
0.1 F
+
47 F
ANALOG
SUPPLY
4.75V–5.25V
0V TO 2.5V
1nF
0.47 F
AD780 2.5V
REFERENCE
25MHz
XO
MCLK
Figure 11. Typical Connection Diagram
Driving the
CONVST Pin
To achieve the specified performance from the AD7485, the
CONVST pin must be driven from a low jitter source. Since the
falling edge on the
CONVST pin determines the sampling instant,
any jitter that may exist on this edge will appear as noise when
the analog input signal contains high frequency components.
The relationship between the analog input frequency (fIN), timing
jitter (tj), and resulting SNR is given by the equation below.
SNR
dB
ft
IN
j
JITTER()
log
()
=
××
10
1
2
π
As an example, if the desired SNR due to jitter was 100 dB with
a maximum full-scale analog input frequency of 500 kHz, ignor-
ing all other noise sources we get an allowable jitter of 3.18 ps
on the
CONVST falling edge. For a 14-bit converter (ideal
SNR = 86.04 dB), the allowable jitter will be greater than the
figure given above; but due consideration needs to be given to the
design of the
CONVST circuitry to achieve 14-bit performance
with large analog input frequencies.
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7490BRU-REEL | IC ADC 12BIT 16CH 28-TSSOP T/R |
| AD7492ARZ-5 | IC ADC 12BIT REF/CLOCK 24SOIC |
| AD7495BRM | IC ADC 12BIT SRL LP W/REF 8MSOP |
| AD75004KP | IC DAC 12BIT QUAD W/BUFF 28-PLCC |
| AD7521LN | CONV D/A 12BIT 1MHZ 2LSB 18-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7490 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP |
| AD7490_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP |
| AD7490BCP | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:12 BIT 16 CHANNEL ADC IC - Bulk 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
| AD7490BCP-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 32-Pin LFCSP EP T/R |
| AD7490BCP-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 32-Pin LFCSP EP T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。