- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄165343 > AD7468BRT (ANALOG DEVICES INC) 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7468BRT |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | MO-178AB, SOT-23, 6 PIN |
| 文件頁(yè)數(shù)： | 8/24頁(yè) |
| 文件大?。?/td> | 327K |
| 代理商： | AD7468BRT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)
–16–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7466/AD7467/AD7468
Digital Inputs
The digital inputs applied to the AD7466/AD7467/
AD7468 are not limited by the maximum ratings which
limit the analog inputs. Instead, the digitals inputs applied
can go to 7V and are not restricted by the VDD + 0.3V
limit as on the analog input. For example, if the AD7466/
AD7467/AD7468 were operated with a VDD of 3V then
5V logic levels could be used on the digital inputs.
However, it is important to note that the data output on
SDATA will still have 3V logic levels when VDD= 3V.
Another advantage of SCLK and
CS not being
restricted by the VDD + 0.3V limit is the fact that power
supply sequencing issues are avoided. If
CS or SCLK are
applied before VDD then there is no risk of latch-up as
there would be on the analog inputs if a signal greater
than 0.3V was applied prior to VDD.
MODE OF OPERATION
The AD7466/AD7467/AD7468 automatically enters
power down at the end of each conversion. This mode of
operation is designed to provide flexible power manage-
ment options and to optimize the power dissipation/
throughput rate ratio for low power applications require-
ments.
Figure 9 shows the general diagram of the
operation for the AD7466/AD7467/AD7468. On the
CS
falling edge the part begins to power up and the Track
and Hold, which was in hold while the part was in power
down, will go into track mode. The conversion is also
initiated at this point. When operating the part with a 3.4
MHz clock it will take 2 clock cycles to fully power up
the part and acquire the input signal. On the third SCLK
falling edge after the
CS falling edge the Track and Hold
will return to hold mode.
For the AD7466 sixteen serial clock cycles are required to
complete the conversion and access the complete conver-
sion result. The AD7466 will automatically enter power
down mode on the 16th SCLK falling edge.
For the AD7467 fourteen serial clock cycles are required
to complete the conversion and access the complete con-
version result. The AD7467 will automatically enter
power down mode on the 14th SCLK falling edge.
Figure 9. Normal Mode Operation
For ac applications, removing high frequency components
from the analog input signal is recommended by use of a
band-pass filter on the relevant analog input pin. In appli-
cations where harmonic distortion and signal to noise
ratio are critical the analog input should be driven from a
low impedance source. Large source impedances will
significantly affect the ac performance of the ADC. This
may necessitate the use of an input buffer amplifier. The
choice of the op amp will be a function of the particular
application.
Table II provides some typical performance data with
various op amps used as the input buffer with a low
frequency analog input under the same set-up conditions.
The AD8631 low power op-amp is ideal for battery-
powered applications. It works from single supply voltages
as low as 1.8V, it has low supply current and the small
package, 5-lead SOT-23, offers considerable space saving
advantages.
When no amplifier is used to drive the analog input the
source impedance should be limited to low values. The
maximum source impedance will depend on the amount of
total harmonic distortion (THD) that can be tolerated. The
THD will increase as the source impedance increases and
performance will degrade. TPC7 shows a graph of the
Total Harmonic Distortion vs. Analog input signal
frequency for different source impedances when using a
supply voltage of TBDV and sampling at a rate of 100
kSPS.
Op amp in the
AD7466 SNR Performance
input buffer
10kHz Input
AD711
TBD dB
AD820
TBD dB
AD8631
TBD dB
Table II. AD7466 performance for various
Input Buffers.
VALID DATA
16
1
THE PART BEGINS
TO POWER UP
3
2
14
12
&6
SCLK
SDATA
AD7468 ENTERS POWER DOWN
&6 CANBEHELDLOW
AD7467 ENTERS POWER DOWN
&6 CANBE HELDLOW
AD7466 ENTERS POWER DOWN
&6 CANBE HELDLOW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7466 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7467 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7468 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD746A | Dual Precision, 500 ns Settling, BiFET Op Amp |
| AD7528BN | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDIP20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7468BRT-R | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7468BRT-R2 | 功能描述:IC ADC 8BIT 1.6V LP SOT-23-6 RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7468BRT-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7468BRT-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7468BRTZ-REEL | 功能描述:IC ADC 8BIT 1.6V LP SOT23-6 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個(gè)單端，雙極；8 個(gè)差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。