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參數(shù)資料
| 型號： | AD7339BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/QUAD DAC 5V W/REF 52-MQFP |
| 標準包裝： | 1 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 8 b |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-QFP |
| 供應(yīng)商設(shè)備封裝： | 52-PQFP（10x10） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD7339BSZ-REELDKR |
–2–
REV. 0
AD7339–SPECIFICATIONS1
Parameter
B Version
Units
Test Conditions/Comments
ADC
ADCCLK = 2.048 MHz
Resolution
8
Bits
Differential Nonlinearity
± 1
LSB max
8 Bits Monotonic
Integral Nonlinearity
± 1
LSB max
Zero Input Offset Error
± 3
LSB
Signal Range
± 1
V max
The input must be biased about 1.4 V. Therefore, ac
coupling with a 1 nF capacitor is needed if the bias
voltage does not equal 1.4 V. The input should be
driven with a maximum source impedance of 50
.
Full Power Input Bandwidth
1.024
MHz
Conversion Rate
2.048
MSPS
Signal to (Noise + Distortion)
42.7
dB min
Effective No. of Bits (ENOB)
6.8
Bits min
Intermodulation Distortion
48
dB min
See Terminology
Error Rate
4.7
× 1011
Input Capacitance
5
pF max
Coding
Offset Binary
00H to FFH with 80H = 0 V
PARALLEL DACS
DACCLK = 2.304 MHz
Resolution
8
Bits
Differential Nonlinearity
± 1
LSB max
8 Bits Monotonic
Integral Nonlinearity
± 1
LSB max
Output Signal Range
VBIAS ± VSWING
VSWING
14/25
× VREFA/B
V nom
VREFA/B means VREFA for DACA and VREFB for DACB.
VBIAS
VREFA/B
V nom
Update Rate
2.304
MHz max
Bipolar Zero Offset Error
±40
mV max
Factory Trim. Does Not Include Gain Error
Gain Error
± 5
% typ
Output Harmonic Content in
50
dB min
For a Full-Scale Digital Sine Wave in Band 0 kHz to 76.8 kHz
Band 0 MHz to 1.152 MHz
46
dB min
For a Full-Scale Digital Sine Wave in Band 0 kHz to 128 kHz
Gain Matching Between DACs
0.2
dB
For Amplitudes Which Equal Full Scale –10 dB
Crosstalk
1.8 k
Load Between DACA and VREFA, and Between
DACB and VREFB
To B Channel from A Channel
55
dB min
A Channel has a full-scale output of frequency 128 kHz.
To A Channel from B Channel
55
dB min
B Channel has a full-scale output of frequency 128 kHz.
To VREFB from A Channel
55
dB min
A Channel has a full-scale output of frequency 128 kHz.
To VREFA from B Channel
55
dB min
B Channel has a full-scale output of frequency 128 kHz.
Load Resistance
1.8
k
min
Connected Between DACA/B and VREFA/B
Load Capacitance
50
pF max
Full-Scale Settling Time
4
s typ
Coding
Offset Binary
00H to FFH with 80H = Bias Voltage
SERIAL DACS
SCLK is a gated 256 kHz clock.
Resolution
8
Bits
Differential Nonlinearity
± 1
LSB
8 Bits Monotonic
Integral Nonlinearity
±1.5
LSB
With Respect to Full Scale
Output Range
See Figure 1
00H
0.2
V max
FFH
AVDD – 0.247
V min
When AVDD > 5.247 V, the analog output will equal 2 VREF.
Update Rate
SCLK/10
kHz max
Load Resistance
20
k
max
Load Capacitance
100
pF max
ISINK
1
mA typ
ISOURCE
100
A typ
Full-Scale Settling Time
2.5
s typ
Coding
Straight Binary
(AVDD = DVDD = +5 V
10%, AGND = DGND = 0 V, TA = TMIN to TMAX, unless other-
wise noted)
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