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參數(shù)資料
| 型號： | AD7339BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 0K |
| 描述： | IC ADC/QUAD DAC 5V W/REF 52-MQFP |
| 標準包裝： | 1 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 8 b |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-QFP |
| 供應商設備封裝： | 52-PQFP（10x10） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD7339BSZ-REELDKR |
AD7339
–9–
REV. 0
FUNCTIONAL DESCRIPTION
A-to-D Converter
The A/D conversion circuitry consists of a track-and-hold ampli-
fier followed by a flash A-to-D converter. Figure 6 shows the
architecture of the ADC.
AIN
D7
D5
D4
D6
D0
D1
D2
D3
AD7339
T/H
HOLD
TIMING AND
CONTROL
LOGIC
ADCCLK ADCPDB
COMPARATOR
NETWORK
DECODE
LOGIC
OUTPUT
REGISTER
OUTPUT
DRIVERS
RESISTOR
LADDER
REFERENCE
Figure 6. ADC Architecture
Track-and-Hold Amplifier
The track-and-hold amplifier on the analog input of the AD7339’s
ADC allows the ADC to accurately convert input frequencies to
8-bit accuracy. The input bandwidth of the track-and-hold am-
plifier is much greater than the Nyquist rate of the ADC.
The operation of the track-and-hold is essentially transparent to
the user. The track-and-hold amplifier goes from its tracking
mode to its hold mode on the rising edge of ADCCLK.
Analog Input
The ADC accepts an analog input of 2 V p-p. The analog input
is biased about 1.4 V internally. If the signal applied to the ADC is
biased about 1.4 V, then dc coupling can be used. AC coupling
is needed if the analog input is biased about any voltage other
than 1.4 V. A capacitor of 1 nF is suitable for ac coupling.
Figure 7 shows the ideal input/output transfer function for the
ADC. The designed code transitions occur midway between
successive integer LSB values (1/2 LSB, 3/2 LSB, 5/2 LSB . . .)
with 1 LSB = FS/256 = 2 V/256 = 7.8 mV.
ADC OUTPUT
CODE
+1V – 1LSB
AD7339
ADC
–1V
0V
01111111
11111110
10000010
10000001
10000000
01111110
00000001
00000000
11111111
ANALOG INPUT VOLTAGE – AIN
Figure 7. ADC Transfer Function
Parallel DACs
The circuitry for each parallel DAC consists of a current source
DAC followed by a buffer that converts the current to a voltage.
Figure 8 shows the functional block diagram for the parallel
DACs.
The loading of both the A and B DAC is controlled by the
DACCLK signal, which is nominally set to 2.304 MHz. The
digital input to each DAC is latched in on the rising edge of the
DACCLK signal so that both DACs simultaneously perform the
D-to-A conversion.
DA7
DA0
VREFB
DACA
AD7339
DAC A
REGISTER
DB7
DB0
DACB
DACCLK
CONTROL
LOGIC
DAC B
REGISTER
REFERENCE
VREFA
DACPDB
DAC A
DAC B
Figure 8. Parallel DACs Functional Block Diagram
The analog output from each DAC is biased about the reference
voltage VREFA (DAC A) or VREFB (DAC B). The analog
output is
±1.4 V about the reference voltage. Since the analog
outputs are biased about the reference voltage, the reference
outputs can be used with the analog outputs to form a differen-
tial signal for the circuitry that follows the DACs.
The AD7339 includes a calibration feature that reduces the
offset between the DAC output bias voltage and the VREFA/
VREFB voltage. A 4-bit offset nulling feature is used to factory
trim the offset. The device also has a 4-bit offset register that is
user controlled; i.e., the user can disable the factory trimmed
offset and use the 4-bit register instead. This allows the user to
calibrate out the system offset; however, the user is also respon-
sible for calibrating out the AD7339 offset.
The 4-bit offset register is accessed via the serial interface that is
used by DAC 0 and DAC 1. Table III gives the addresses for
accessing these registers. D5 of the 10-bit data word enables the
user to write to the 4-bit offset register. When this bit is set to 0,
the factory trimmed value is used as the offset value, while the
user programmed value is used when D5 equals 1. When the
offset is user controlled, D4 is used to inform the AD7339 to
reduce or increase the DAC output voltage. When D4 equals 0,
the DAC output is reduced, while the DAC output is increased
when D4 equals 1. When user trimming is being used, the 4-bit
word to be loaded into the register is contained in the 4 LSBs of
the 10-bit word being written to the serial port.
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