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參數(shù)資料
| 型號： | AD7339BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/QUAD DAC 5V W/REF 52-MQFP |
| 標準包裝： | 1 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 8 b |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-QFP |
| 供應商設備封裝： | 52-PQFP（10x10） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD7339BSZ-REELDKR |
AD7339
–7–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Function
Power Supply
33
AVDD
Analog power supply connection.
2
DVDD1
Digital power supply for the parallel DACs.
12
DGND1
Digital ground connection for the parallel DACs.
36
AGND1
Analog ground connection for the parallel DACs.
22
DVDD2
Digital power supply for the ADC.
29
DVDD3
Digital power supply for the ADC.
21
DGND2
Digital ground connection for the ADC.
28
DGND3
Digital ground connection for the ADC.
32
AGND2
Analog ground connection for the ADC.
34
AGND3
Analog ground connection for the reference.
ADCs
31
AIN
Analog input to the ADC. The analog input must be appropriately ac coupled.
The AD7339 can accept an analog input of
±1 V maximum.
27
ADCCLK
ADC Input Clock, CMOS Logic Input. The analog input is sampled on the rising edge
of ADCCLK. ADCCLK is nominally set to 2.048 MHz.
26–23, 20–17
D0–D7
Digital Output from the ADC. The 8-bit digital word from the ADC is in offset binary.
The digital output uses CMOS logic.
30
ADCPDB
Digital Input. When ADCPDB is low, the ADC is powered down. While in this mode,
ADCCLK should be tied low. The ADC is powered up by taking ADCPDB high.
Parallel DACs
45–52
DA0–DA7
Digital input to the parallel A DAC. The digital input uses CMOS logic and the word
is presented to the DAC in offset binary format.
3–10
DB0–DB7
Digital input to the parallel B DAC. The digital input uses CMOS logic and the word
is presented to the DAC in offset binary format.
1
DACCLK
Input clock to the parallel DACs. The digital words in the A and B DAC registers are
loaded into the DACs on the rising edge of DACCLK. DACCLK has a nominal fre-
quency of 2.304 MHz and uses CMOS logic.
43, 41
DACA, DACB
Analog outputs from the A and B DACs. Both DACs have an analog output of VREFA/
VREFB
± X volts where VREFA = VREFB = 2.5 V nominal and X = 1.4 V.
PIN CONFIGURATION
14 15 16 17 18 19 20 21 22 23 24 25 26
1
2
3
4
5
6
7
8
9
10
11
13
12
52 51 50 49 48
43 42 41 40
47 46 45 44
39
38
37
36
35
34
33
32
31
30
29
28
27
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
VREFA
DACA
VREFB
DACB
SDAC1S
DACCLK
DVDD1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DACPDB
DGND1
SDACPDB
SDAC1F
SDAC0S
SDAC0F
AGND1
VREF
AGND3
AVDD
AGND
AIN
ADCPDB
DVDD3
DGND3
ADCCLK
SCLK
LATCH
SDATA
D7
D6
D5
D4
DGND2
DVDD2
D3
D1
D0
D2
AD7339
2
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