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參數(shù)資料
型號: AD73360ASUZ
廠商: Analog Devices Inc
文件頁數(shù): 32/35頁
文件大小: 0K
描述: IC ANALOG FRONT END 6CH 44-TQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 16
通道數(shù): 6
功率(瓦特): 80mW
電壓 - 電源,模擬: 2.7 V ~ 3.3 V
電壓 - 電源,數(shù)字: 2.7 V ~ 3.3 V
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
REV. A
AD73360
–6–
TIMING CHARACTERISTICS
Limit at
Parameter
TA = –40 C to +85 C
Unit
Description
Clock Signals
See Figure 1
t1
61
ns min
MCLK Period
t2
24.4
ns min
MCLK Width High
t3
24.4
ns min
MCLK Width Low
Serial Port
See Figures 3 and 4
t4
t1
ns min
SCLK Period
t5
0.4
× t1
ns min
SCLK Width High
t6
0.4
× t
1
ns min
SCLK Width Low
t7
20
ns min
SDI/SDIFS Setup Before SCLK Low
t8
0
ns min
SDI/SDIFS Hold After SCLK Low
t9
10
ns max
SDOFS Delay from SCLK High
t10
10
ns min
SDOFS Hold After SCLK High
t11
10
ns min
SDO Hold After SCLK High
t12
10
ns max
SDO Delay from SCLK High
t13
30
ns max
SCLK Delay from MCLK
(AVDD = 3 V
10%; DVDD = 3 V
10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise
noted)
TIMING CHARACTERISTICS
Limit at
Parameter
TA = –40 C to +85 C
Unit
Description
Clock Signals
See Figure 1
t1
61
ns min
MCLK Period
t2
24.4
ns min
MCLK Width High
t3
24.4
ns min
MCLK Width Low
Serial Port
See Figures 3 and 4
t4
t1
ns min
SCLK Period
t5
0.4
× t
1
ns min
SCLK Width High
t6
0.4
× t1
ns min
SCLK Width Low
t7
20
ns min
SDI/SDIFS Setup Before SCLK Low
t8
0
ns min
SDI/SDIFS Hold After SCLK Low
t9
10
ns max
SDOFS Delay from SCLK High
t10
10
ns min
SDOFS Hold After SCLK High
t11
10
ns min
SDO Hold After SCLK High
t12
10
ns max
SDO Delay from SCLK High
t13
30
ns max
SCLK Delay from MCLK
(AVDD = 5 V
10%; DVDD = 5 V
10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise
noted)
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