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參數(shù)資料
| 型號： | AD73360ASUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANALOG FRONT END 6CH 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 6 |
| 功率（瓦特）： | 80mW |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.3 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.3 V |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
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REV. A
–3–
AD73360
AD73360A
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS
VINH, Input High Voltage
VDD – 0.8
VDD
V
VINL, Input Low Voltage
0
0.8
V
IIH, Input Current
10
A
CIN, Input Capacitance
10
pF
LOGIC OUTPUTS
VOH, Output High Voltage
VDD – 0.4
VDD
V
|IOUT|
≤ 100 A
VOL, Output Low Voltage
0
0.4
V
|IOUT|
≤ 100 A
Three-State Leakage Current
–10
+10
A
POWER SUPPLIES
AVDD1, AVDD2
2.7
3.3
V
DVDD
2.7
3.3
V
IDD
8
See Table I
NOTES
1Operating temperature range is as follows: –40
°C to +85°C. Therefore, T
MIN = –40
°C and T
MAX = +85
°C.
2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4
× 1011)/DMCLK.
7Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = DVDD = 3.3 V)
Total
Analog
Digital
Current
MCLK
Conditions
Current
(Max)
SE
ON
Comments
ADCs Only On
12
10
26.5
1
YES
REFOUT Disabled
REFCAP Only On
0.75
0.04
1.0
0
NO
REFOUT Disabled
REFCAP and
REFOUT Only On
3.3
0.04
4.5
0
NO
All Sections Off
0.01
1.2
1.5
0
YES
MCLK Active Levels Equal to 0 V and DVDD
All Sections Off
0.01
0.03
0.1
0
NO
Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
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| AD73360ASUZ-REEL | 功能描述:IC ANALOG FRONT END 6CH 44-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360EZEVAL | 制造商:AD 功能描述:73360 ANALOG DEVICE S7L3A |
| AD73360EZ-EVAL | 制造商:AD 功能描述:73360 ANALOG DEVICE S7L3A |
| AD73360L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Six-Input Channel Analog Front End |
| AD73360LAR | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 28-Pin SOIC W 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
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