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參數(shù)資料
| 型號(hào)： | AD73360ARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONTEND 6CH 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 6 |
| 功率（瓦特）： | 80mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
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REV. A
AD73360
–21–
INTERFACING
The AD73360 can be interfaced to most modern DSP engines
using conventional serial port connections and an extra enable
control line. Both serial input and output data use an accompa-
nying frame synchronization signal which is active high one
clock cycle before the start of the 16-bit word or during the last
bit of the previous word if transmission is continuous. The serial
clock (SCLK) is an output from the AD73360 and is used to
define the serial transfer rate to the DSP’s Tx and Rx ports.
Two primary configurations can be used: the first is shown in
Figure 11 where the DSP’s Tx data, Tx frame sync, Rx data and
Rx frame sync are connected to the AD73360’s SDI, SDIFS,
SDO and SDOFS respectively. This configuration, referred to
as indirectly coupled or nonframe sync loop-back, has the effect
of decoupling the transmission of input data from the receipt of
output data. When programming the DSP serial port for this
configuration, it is necessary to set the Rx frame sync as an
input to the DSP and the Tx frame sync as an output generated
by the DSP. This configuration is most useful when operating in
mixed mode, as the DSP has the ability to decide how many
words can be sent to the AD73360(s). This means that full con-
trol can be implemented over the device configuration in a given
sample interval. The second configuration (shown in Figure 12)
has the DSP’s Tx data and Rx data connected to the AD73360’s
SDI and SDO, respectively, while the DSP’s Tx and Rx frame
syncs are connected to the AD73360’s SDIFS and SDOFS. In
this configuration, referred to as directly coupled or frame sync
loop-back, the frame sync signals are connected together and
the input data to the AD73360 is forced to be synchronous with
the output data from the AD73360. The DSP must be pro-
grammed so that both the Tx and Rx frame syncs are inputs as
the AD73360’s SDOFS will be input to both. This configura-
tion guarantees that input and output events occur simulta-
neously and is the simplest configuration for operation in normal
Data Mode. Note that when programming the DSP in this
configuration it is advisable to preload the Tx register with the
first control word to be sent before the AD73360 is taken out of
reset. This ensures that this word will be transmitted to coincide
with the first output word from the device(s).
Digital Interfacing
The AD73360 is designed to easily interface to most common
DSPs. The SCLK, SDO, SDOFS, SDI and SDIFS must be
connected to the SCLK, DR, RFS, DT and TFS pins of the
DSP respectively. The SE pin may be controlled from a parallel
output pin or flag pin such as FL0–2 on the ADSP-21xx (or XF
on the TMS320C5x) or, where SPORT power-down is not
required, it can be permanently strapped high using a suitable
pull-up resistor. The
RESET pin may be connected to the sys-
tem hardware reset structure or it may also be controlled using a
dedicated control line. In the event of tying it to the global
system reset, it is necessary to operate the device in mixed
mode, which allows a software reset, otherwise there is no con-
venient way of resetting the device. Figures 11 and 12 show
typical connections to an ADSP-2181 while Figures 13 and 14
show typical connections to an ADSP-21xx and a TMS320C5x,
respectively.
TFS
DT
SCLK
DR
RFS
ADSP-21xx
DSP
AD73360
SDIFS
SDI
SCLK
SDO
SDOFS
Figure 11. Indirectly Coupled or Nonframe Sync Loop-
Back Configuration
TFS
DT
SCLK
DR
RFS
ADSP-21xx
DSP
AD73360
SDIFS
SDI
SCLK
SDO
SDOFS
Figure 12. Directly Coupled or Frame Sync Loop-
Back Configuration
TFS
DT
SCLK
DR
RFS
ADSP-21xx
DSP
AD73360
ANALOG
FRONT-END
SDIFS
SDI
SCLK
SDO
SDOFS
FL0
FL1
RESET
SE
Figure 13. AD73360 Connected to ADSP-21xx
FSX
DX
CLKX
CLKR
DR
TMS320C5x
DSP
AD73360
ANALOG
FRONT-END
SDIFS
SDI
SCLK
SDO
SDOFS
FSR
XF
RESET
SE
Figure 14. AD73360 Connected to TMS320C5x
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD73360ARZ | 制造商:Analog Devices 功能描述:ANALOG FRONT END 6 CH 28SOIC |
| AD73360ARZ-REEL | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360ARZ-REEL7 | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360ASU | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 44-Pin TQFP 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
| AD73360ASU-REEL | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 44-Pin TQFP T/R |
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