參數(shù)資料
型號(hào)： AD73360ARZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/35頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR FRONTEND 6CH 28SOIC
標(biāo)準(zhǔn)包裝： 27
位數(shù)： 16
通道數(shù)： 6
功率（瓦特）： 80mW
電壓 - 電源，模擬： 3V
電壓 - 電源，數(shù)字： 3V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
REV. A
AD73360
–18–
Control Register C
CRC:0
Global Power-Up. Writing a 1 to this bit will cause all six channels of the AD73360 to power-up regardless of the
status of the Power Control Bits in CRD-CRF. If less than six channels are required, this bit should be set to 0 and
the Power Control Bits of the relevant channels should be set to 1.
CRC:1–4
Reserved. These bits are reserved and should be programmed to 0 to ensure correct operation.
CRC:5
Power-Up Reference. This bit controls the state of the on-chip reference. A 1 in this bit will power up the refer-
ence. A 0 in this bit will power-down the reference. Note that the reference is automatically powered up if any
channel is enabled.
CRC:6
Reference Output. When this bit is set to 1, the REFOUT pin is enabled.
CRC:7
5 V Enable. When this bit is set to 1, the 5 V operating mode is enabled.
Control Register D
CRD:0–2
Input Gain Selection. These bits select the input gain for ADC1. See Table IV.
CRD:3
Power Control for ADC1. A 1 in this bit powers up ADC1.
CRD:4–6
Input Gain Selection. These bits select the input gain for ADC2. See Table IV.
CRD:7
Power Control for ADC2. A 1 in this bit powers up ADC2.
Control Register E
CRE:0-2
Input Gain Selection. These bits select the input gain for ADC3. See Table IV.
CRE:3
Power Control for ADC3. A 1 in this bit powers up ADC3.
CRE:4–6
Input Gain Selection. These bits select the input gain for ADC4. See Table IV.
CRE:7
Power Control for ADC4. A 1 in this bit powers up ADC4.
Control Register F
CRF:0–2
Input Gain Selection. These bits select the input gain for ADC5. See Table IV.
CRF:3
Power Control for ADC5. A 1 in this bit powers up ADC5.
CRF:4–6
Input Gain Selection. These bits select the input gain for ADC6. See Table IV.
CRF:7
Power Control for ADC6. A 1 in this bit powers up ADC6.
Control Register G
CRG:0–5
Channel Select. These bits are used in association with CRG:6 and CRG:7. If the Reset Analog Modulator bit
(CRG:6) is 1, then a 1 in a Channel Select bit location will reset the Analog Modulator for that channel. If the
Single-Ended Enable Mode bit (CRG:7) is 1, then a 1 in a Channel Select bit location will put that channel into
Single-Ended Mode. If any channel has its Channel Select bit set to 0, the channel will be set for Differentially-
Ended Mode and will not have its analog modulator reset regardless of the state of CRG:6 and CRG:7.
CRG:6
Reset Analog Modulator. Setting this bit to a 1 will reset the Analog Modulators for any channel whose Channel
Select bit (CRG:0–5) is set to 1. This bit should be set to 0 for normal operation.
CRG:7
Single-Ended Enable Mode. Setting this bit to a 1 will enable Single-Ended Mode on any channel whose Channel
Select bit (CRG:0–5) is set to 1. Setting this bit to 0 will select Differentially-Ended Input Mode for all channels.
Control Register H
CRH:0–5
Invert Select. These bits are used in association with CRH:7. If the Enable Invert Channel Mode bit (CRH:7) is 1,
then a 1 in a Channel Select bit location will put that channel into Inverted Mode. If any channel has its Channel
Select bit set to 0, the channel will not be inverted regardless of the state CRH:7.
CRH:6
Test Mode Enable. This bit should be set to 0 to ensure normal operation.
CRH:7
Enable Invert Channel Mode. Setting this bit to a 1 will enable invert any channel whose Channel Select bit
(CRH:0–5) is set to 1. Setting this bit to 0 will select Noninverted (Normal) Mode for all channels.
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