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參數(shù)資料
| 型號(hào)： | AD73311LARUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END LP 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 2 |
| 功率（瓦特）： | 50mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
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AD73311
–17–
REV. B
Table XI. Control Register A Description
CONTROL REGISTER A
765
432
10
RESET
DC2
DC1
DC0
DLB
ALB
MM
DATA/
PGM
Bit
Name
Description
0
DATA/
PGM
Operating Mode (0 = Program; 1 = Data Mode)
1
MM
Mixed Mode (0 = Off; 1 = Enabled)
2
ALB
Analog Loop-Back Mode (0 = Off; 1 = Enabled)
3
DLB
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
4
DC0
Device Count (Bit 0)
5
DC1
Device Count (Bit 1)
6
DC2
Device Count (Bit 2)
7
RESET
Software Reset (0 = Off; 1 = Initiates Reset)
Table XII. Control Register B Description
CONTROL REGISTER B
765
432
10
CEE
MCD2
MCD1
MCD0
SCD1
SCD0
1
Bit
Name
Description
0
Reserved
Must Be Programmed to 1
1
Reserved
Must Be Programmed to 1
2
SCD0
Serial Clock Divider (Bit 0)
3
SCD1
Serial Clock Divider (Bit 1)
4
MCD0
Master Clock Divider (Bit 0)
5
MCD1
Master Clock Divider (Bit 1)
6
MCD2
Master Clock Divider (Bit 2)
7
CEE
Control Echo Enable (0 = Off; 1 = Enabled)
Table XIII. Control Register C Description
CONTROL REGISTER C
765
4321
0
5VEN
RU
PUREF
PUDAC PUADC
0
PU
Bit
Name
Description
0
PU
Power-Up Device (0 = Power Down; 1 = Power On)
1
Reserved
Must Be Programmed to 0
2
Reserved
Must Be Programmed to 0
3
PUADC
ADC Power (0 = Power Down; 1 = Power On)
4
PUDAC
DAC Power (0 = Power Down; 1 = Power On)
5
PUREF
REF Power (0 = Power Down; 1 = Power On)
6
RU
REFOUT Use (0 = Disable REFOUT; 1 = Enable
REFOUT)
7
5VEN
Enable 5 V Operating Mode (0 = Disable 5 V Mode;
1 = Enable 5 V Mode)
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