t1 t2 t
參數(shù)資料
型號: AD73311LARUZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 34/36頁
文件大?。?/td> 0K
描述: IC PROCESSOR FRONT END LP 20SSOP
標準包裝: 1,000
位數(shù): 16
通道數(shù): 2
功率(瓦特): 50mW
電壓 - 電源,模擬: 3V
電壓 - 電源,數(shù)字: 3V
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 20-SSOP
包裝: 帶卷 (TR)
AD73311
–7–
REV. B
t1
t2
t3
Figure 1. MCLK Timing
TIMING CHARACTERISTICS
Limit at
Parameter
TA = –40 C to +85 C
Unit
Description
Clock Signals
See Figure 1
t1
61
ns min
MCLK Period
t2
24.4
ns min
MCLK Width High
t3
24.4
ns min
MCLK Width Low
Serial Port
See Figures 3 and 4
t4
t1
ns min
SCLK Period
t5
0.4
× t1
ns min
SCLK Width High
t6
0.4
× t1
ns min
SCLK Width Low
t7
20
ns typ
SDI/SDIFS Setup Before SCLK Low
t8
0
ns typ
SDI/SDIFS Hold After SCLK Low
t9
10
ns typ
SDOFS Delay from SCLK High
t10
10
ns typ
SDOFS Hold After SCLK High
t11
10
ns typ
SDO Hold After SCLK High
t12
10
ns typ
SDO Delay from SCLK High
t13
30
ns typ
SCLK Delay from MCLK
(AVDD = +5 V
10%; DVDD = +5 V
10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless
otherwise noted)
100 AIOL
100 AIOH
CL
15pF
+2.1V
TO OUTPUT
PIN
Figure 2. Load Circuit for Timing Specifications
t1
t2
t3
t13
t5
t6
t4
MCLK
SCLK
*
SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
*
Figure 3. SCLK Timing
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