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| 型號： | AD7328BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/37頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT+SAR 8CHAN 20-TSSOP |
| 設(shè)計資源： | Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | iCMOS® |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極 |
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Data Sheet
AD7328
Rev. C | Page 17 of 36
D
VDD
C2
R1
VIN+
VSS
C1
D
VDD
C2
R1
VIN–
VSS
C1
04852-
024
Figure 30. Equivalent Analog Input Circuit, Differential Mode
Care should be taken to ensure that the analog input does
not exceed the VDD and VSS supply rails by more than 300 mV.
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the VDD supply rail
or the VSS supply rail. These diodes can conduct up to 10 mA
without causing irreversible damage to the part.
In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
Track-and-Hold Section
The track-and-hold on the analog input of the AD7328 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the track-
and-hold is greater than the Nyquist rate of the ADC. The AD7328
can handle frequencies up to 22 MHz.
The track-and-hold enters its tracking mode on the 14th SCLK
rising edge after the CS falling edge. The time required to acquire
an input signal depends on how quickly the sampling capacitor
is charged. With zero source impedance, 305 ns is sufficient to
acquire the signal to the 13-bit level. The acquisition time for
the ±10 V, ±5 V, and 0 V to +10 V ranges to settle to within
± LSB is typically 200 ns.
The acquisition time required is calculated using the following
formula:
tACQ = 10 × ((RSOURCE + R) C)
where C is the sampling capacitance, and R is the resistance
seen by the track-and-hold amplifier looking at the input.
For the AD7328, the value of R includes the on resistance of the
input multiplexer and is typically 300 . RSOURCE should include
any extra source impedance on the analog input.
When the AD7328 is run at a throughput rate of 1 MSPS with a
20 MHz SCLK signal, the ADC has approximately
1.5 SCLK + t8 + tQUIET
to acquire the analog input signal. The ADC goes back into
hold mode on the CS falling edge.
As the VDD/VSS supply voltage is reduced, the on resistance of
the input multiplexer increases. Therefore, based on the equation
for tACQ, it is necessary to increase the acquisition time provided
to the AD7328 and, hence, decrease the overall throughput rate.
Figure 31 shows that if the throughput rate is reduced when
operating with minimum VDD and VSS supplies, the specified
THD performance is maintained.
–50
–95
5
19
04852-
051
±VDD/VSS SUPPLIES (V)
T
HD
(
d
B)
–55
–60
–65
–70
–75
–80
–85
–90
7
9
11
13
15
17
500kSPS
750kSPS
1MSPS
VCC = VDRIVE = 5V
INTERNAL REFERENCE
TA = 25°C
FIN = 10kHz
±5V RANGE
SE MODE
Figure 31. THD vs. ±VDD/VSS Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS
Unlike other bipolar ADCs, the AD7328 does not have a
resistive analog input structure. On the AD7328, the bipolar
analog signal is sampled directly onto the sampling capacitor.
This gives the AD7328 high analog input impedance. The
analog input impedance can be calculated from the following
formula:
Z = 1/(fS × CS)
where fS is the sampling frequency, and CS is the sampling
capacitor value.
CS depends on the analog input range chosen (see the
Specifications section). When operating at 1 MSPS, the analog
input impedance is typically 75 kΩ for the ±10 V range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases, the
current required to drive the analog input therefore decreases.
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