參數(shù)資料
型號： AD7265BSUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 9/29頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 3CHAN 1MSPS 32TQFP
設(shè)計(jì)資源： AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
標(biāo)準(zhǔn)包裝： 500
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 21mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 12 個(gè)單端，單極；6 個(gè)差分，單極；6 個(gè)偽差分，單極
AD7265
Rev. A | Page 16 of 28
Using an Op Amp Pair
Pseudo Differential Mode
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7265. The
circuit configurations illustrated in
The AD7265 can have a total of six pseudo differential pairs. In
this mode, VIN+ is connected to the signal source that must have
an amplitude of V
show how a dual op amp can be used to convert a single-ended
signal into a differential signal for both a bipolar and unipolar
input signal, respectively.
(or 2 × V
REF
, depending on the range
chosen) to make use of the full dynamic range of the part. A dc
input is applied to the VIN pin. The voltage applied to this input
provides an offset from ground or a pseudo ground for the VIN+
input. The benefit of pseudo differential inputs is that they
separate the analog input signal ground from the ADC’s ground
allowing dc common-mode voltages to be cancelled. The typical
voltage range for the V
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a
suitable dual op amp that can be used in this configuration to
provide differential drive to the AD7265.
IN
pin, while in pseudo differential
mode, is shown in Figure 28 and Figure 29. Figure 30 shows a
connection diagram for pseudo differential mode.
04674-
043
VREF (V)
3.0
0
0.5
1.0
1.5
2.0
2.5
V
IN
–(V)
1.0
0.8
0.4
0.6
0.2
–0.2
0
–0.4
TA = 25°C
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 26 and Figure 27 are optimized for
dc coupling applications requiring best distortion performance.
The circuit configuration shown in Figure 26 converts a
unipolar, single-ended signal into a differential signal.
The differential op amp driver circuit shown in Figure 27 is
configured to convert and level shift a single-ended, ground-
referenced (bipolar) signal to a differential signal centered at the
V
level of the ADC.
REF
GND
2 × VREF p-p
27
V+
V–
V+
V–
VREF
2.5V
3.75V
1.25V
2.5V
3.75V
1.25V
DCAPA/DCAPB
VIN+
VIN–
440
220
0.47F
1ADDITIONAL PINS OMITTED FOR CLARITY.
220
10k
A
0467
4-
023
AD72651
Figure 28. VIN Input Voltage Range vs. VREF in
Pseudo Differential Mode with VDD = 3 V
046
74-
044
VREF (V)
5.0
0
0.51.01.52.02.5
3.0
3.54.04.5
V
IN
–(V)
2.5
2.0
1.5
1.0
0.5
0
–0.5
TA = 25°C
Figure 26. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
into a Differential Signal
20k
220k
2 × VREF p-p
27
V+
V–
V+
V–
GND
2.5V
3.75V
1.25V
2.5V
3.75V
1.25V
DCAPA/DCAPB
VIN+
VIN–
440
220
0.47F
1ADDITIONAL PINS OMITTED FOR CLARITY.
220
10k
A
0467
4-
024
AD72651
Figure 29. VIN Input Voltage Range vs. VREF in
Pseudo Differential Mode with VDD = 5 V
DC INPUT
VOLTAGE
VREF
p–p
VREF
VIN+
VIN–
0.47F
1ADDITIONAL PINS OMITTED FOR CLARITY.
0467
4-
0
25
AD72651
Figure 27. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
Figure 30. Pseudo Differential Mode Connection Diagram
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