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參數(shù)資料
| 型號： | AD7265BSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 3CHAN 1MSPS 32TQFP |
| 設計資源： | AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048) |
| 標準包裝： | 500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 21mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 12 個單端，單極；6 個差分，單極；6 個偽差分，單極 |
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AD7265
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = TMAX to TMIN, unless otherwise noted1.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK2
1
MHz min
TA = 40°C to +85°C
4
MHz min
TA > 85°C to 125°C
16
MHz max
tCONVERT
14 × tSCLK
ns max
tSCLK = 1/fSCLK
875
ns max
fSCLK = 16 MHz
tQUIET
30
ns min
Minimum time between end of serial read and next falling edge of CS
t2
15/20
ns min
VDD = 5 V/3 V, CS to SCLK setup time, TA = 40°C to +85°C
20/30
ns min
VDD = 5 V/3 V, CS to SCLK setup time, TA > 85°C to 125°C
t3
15
ns max
Delay from CS until DOUTA and DOUTB are three-state disabled
t43
36
ns max
Data access time after SCLK falling edge, VDD = 3 V
27
ns max
Data access time after SCLK falling edge, VDD = 5 V
t5
0.45 tSCLK
ns min
SCLK low pulse width
t6
0.45 tSCLK
ns min
SCLK high pulse width
t7
10
ns min
SCLK to data valid hold time, VDD = 3 V
5
ns min
SCLK to data valid hold time, VDD = 5 V
t8
15
ns max
CS rising edge to DOUTA, DOUTB, high impedance
t9
30
ns min
CS rising edge to falling edge pulse width
t10
5
ns min
SCLK falling edge to DOUTA, DOUTB, high impedance
50
ns max
SCLK falling edge to DOUTA, DOUTB, high impedance
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Serial
2 Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
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