- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗1980 > AD7262BSTZ (Analog Devices Inc)IC ADC 2CH 12BIT PGA/COM 48LQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD7262BSTZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 31/33闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 2CH 12BIT PGA/COM 48LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 1M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 2 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 120mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 105°C |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 48-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 48-LQFP锛�7x7锛� |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤�(l猫i)鍨嬶細 | 2 鍊�(g猫)宸垎锛屽柈妤� |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)鐣�(d膩ng)鍓嶇31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)
AD7262
Rev. 0 | Page 6 of 32
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VREF = 2.5 V internal/external; TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Limit at TMIN, TMAX
Parameter
2.7 V 鈮� VDRIVE 鈮� 3.6 V
4.75 V 鈮� VDRIVE 鈮� 5.25 V
Unit
Description
fSCLK
200
kHz min
40
MHz max
32
MHz typ
20
MHz max
AD7262-5
tCONVERT
19 脳 tSCLK
ns max
tSCLK = 1/fSCLK
475
ns max
AD7262
950
ns max
AD7262-5
tQUIET
13
ns min
Minimum time between end of serial read/bus relinquish
and next falling edge of CS
t2
10
ns min
CS to SCLK setup time
15
ns max
Delay from 19th SCLK falling edge until DOUTA and DOUTB are
three-state disabled
t4
29
23
ns max
Data access time after SCLK falling edge
t5
15
13
ns min
SCLK to data valid hold time
t6
0.4 脳 tSCLK
ns min
SCLK high pulse width
t7
0.4 脳 tSCLK
ns min
SCLK low pulse width
t8
13
ns min
CS rising edge to falling edge pulse width
t9
13
ns max
CS rising edge to DOUTA, DOUTB, high impedance/bus
relinquish
t10
5
ns min
SCLK falling edge to DOUTA, DOUTB, high impedance
35
ns max
SCLK falling edge to DOUTA, DOUTB, high impedance
t11
2
渭s min
Minimum CAL pin high time
t12
2
渭s min
Minimum time between the CAL pin high and the CS
falling edge
t13
3
ns min
DIN setup time prior to SCLK falling edge
t14
3
ns min
DIN hold time after SCLK falling edge
tPOWER-UP
240
渭s max
Internal reference, with a 1 渭F decoupling capacitor
15
渭s max
With an external reference, 10 渭s typical
SCLK
15
19
DOUTA
THREE-STATE
t4
23
4
20
t5
THREE-
STATE
t7
t3
18
DB9A
DB10A
DB11A
21
29
30
31
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVCC) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
Terminology section.
2 See the Serial Interface section.
3 The time required for the output to cross 0.4 V or 2.4 V.
TIMING DIAGRAM
CS
DB1A
DB0A
t2
t9
tQUIET
t8
t6
DOUTB
THREE-STATE
THREE-
STATE
DB9B
DB10B
DB11B
DB1B
DB0B
076
06
-00
2
Figure 2. Serial Interface Timing Diagram
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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