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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD7262BSTZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 28/33闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC 2CH 12BIT PGA/COM 48LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 1M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 2 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 120mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 105°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 48-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 48-LQFP锛�7x7锛� |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 2 鍊�(g猫)宸垎锛屽柈妤� |
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AD7262
Rev. 0 | Page 3 of 32
SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 1 MSPS and fSCLK = 40 MHz
for AD7262, fSAMPLE = 500 kSPS and fSCLK = 20 MHz for AD7262-5, VREF = 2.5 V internal/external; TA = 40掳C to +105掳C, unless
otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE1
fIN = 100 kHz sine wave
Signal-to-Noise Ratio (SNR)2
70
73
dB
PGA gain setting = 2
Signal-to-(Noise + Distortion) Ratio
70
72
dB
Total Harmonic Distortion (THD)2
85
77
dB
Spurious-Free Dynamic Range (SFDR)2
97
dB
Common-Mode Rejection Ratio (CMRR)3
76
dB
For PGA gain setting = 2, ripple
frequency of 50 Hz/60 Hz; see Figure 17
and Figure 18
ADC-to-ADC Isolation3
90
dB
1.2
MHz
@ 3 dB; PGA gain setting = 128
1.7
MHz
@ 3 dB; PGA gain setting = 2
DC ACCURACY
Resolution
12
Bits
Integral Nonlinearity2
卤0.5
卤1
LSB
Differential Nonlinearity2
卤0.5
卤0.99
LSB
Guaranteed no missed codes to 12 bits
Positive Full-Scale Error2
卤0.122
卤0.305
% FSR
Pregain calibration
卤0.018
% FSR
Postgain calibration
Positive Full-Scale Error Match
卤0.061
% FSR
Zero Code Error2
卤0.092
卤0.244
% FSR
Preoffset and pregain calibration
卤0.012
% FSR
Postoffset and postgain calibration
Zero Code Error Match
卤0.061
% FSR
Negative Full-Scale Error2
卤0.122
卤0.305
% FSR
Pregain calibration
卤0.018
% FSR
Postgain calibration
Negative Full-Scale Error Match
卤0.061
% FSR
Zero Code Error Drift
2.5
渭V/掳C
ANALOG INPUT
Input Voltage Range, VIN+ and VIN
Gain
2
V
REF
CM
脳
卤
V
VCM = AVCC/2; PGA gain setting 鈮� 2
Common-Mode Voltage Range, VCM
VCM 100 mV
VCM + 100 mV
V
VCM = 2; PGA gain setting = 1;
(VCC/2) 0.4
(VCC/2) + 0.2
V
VCM = AVCC/2; PGA gain setting = 2
(VCC/2) 0.4
(VCC/2) + 0.4
V
VCM = AVCC/2; 3 鈮� PGA gain setting 鈮� 32
(VCC/2) 0.6
(VCC/2) + 0.8
V
VCM = AVCC/2; PGA gain setting 鈮� 48
DC Leakage Current
卤0.001
卤1
渭A
Input Capacitance3
5
pF
Input Impedance3
1
G惟
REFERENCE INPUT/OUTPUT
Reference Output Voltage5
2.495
2.5
2.505
V
2.5 V 卤 5 mV max @ 25掳C
Reference Input Voltage Range
2.5
V
DC Leakage Current
卤0.3
卤1
渭A
External reference applied to
Pin VREFA/Pin VREFB
Input Capacitance3
20
pF
4
惟
Reference Temperature Coefficient
20
ppm/掳C
VREF Noise3
20
渭V rms
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