PD0/DIN Logic Input/Data Input. Places the" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD7262BSTZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 2/33闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ADC 2CH 12BIT PGA/COM 48LQFP
妯欐簴鍖呰锛� 1
浣嶆暩(sh霉)锛� 12
閲囨ǎ鐜囷紙姣忕锛夛細 1M
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI?
杞夋彌鍣ㄦ暩(sh霉)鐩細 2
鍔熺巼鑰楁暎锛堟渶澶э級锛� 120mW
闆诲闆绘簮锛� 鍠浕婧�
宸ヤ綔婧害锛� -40°C ~ 105°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 48-LQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 48-LQFP锛�7x7锛�
鍖呰锛� 绠′欢
杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� 2 鍊嬪樊鍒�锛屽柈妤�
AD7262
Rev. 0 | Page 9 of 32
Pin No.
Mnemonic
Description
23
PD0/DIN
Logic Input/Data Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction
with the PD2 and PD1 pins (see Table 7). If all gain selection pins, G0 to G3, are tied low, this pin acts
as the data input pin, and all programming is via the control register (see Table 8). Data to be written
to the AD7262/AD7262-5 control register is provided on this input and is clocked into the register
on the falling edge of SCLK.
35
CS
Chip Select. Active low logic input. This input initiates conversions on the AD7262/AD7262-5.
48, 47, 46, 45
CA+, CA,
CB+, CB
Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A
and Comparator B. These two comparators have very low power consumption.
13, 14, 15, 16
CC+, CC,
CD+, CD
Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C
and Comparator D. This pair of comparators offers very fast propagation delays.
5, 6, 8, 19, 42
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7262/AD7262-5. All
analog input signals and any external reference signal should be referred to this AGND voltage.
All AGND pins should connect to the AGND plane of a system. The AGND, DGND, CA_CB_GND, and
CC_CD_GND voltages ideally should be at the same potential and must not be more than 0.3 V apart,
even on a transient basis. CA_CB_GND and CC_CD_GND can be tied to AGND.
28
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7262/AD7262-5.
The DGND pin should be connected to the DGND plane of a system. The DGND and AGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
30, 29, 26, 25
COUTA, COUTB,
COUTC, COUTD
Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective
comparator. These are digital output pins with logic levels determined by the VDRIVE supply.
32, 31
DOUTA, DOUTB
Serial Data Outputs. The data output from the AD7262/AD7262-5 is supplied to each pin as a serial
data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK
input. A total of 31 SCLKs is required to perform the conversion and access the 12-bit data. During
the conversion process, the data output pins are in three-state and, when the conversion is
completed, the 19th SCLK edge clocks out the MSB. The data simultaneously appears on both pins
from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for
an additional 12 SCLK cycles on either DOUTA or DOUTB following the initial 31 SCLKs, the data from
the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both
ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port.
40, 39, 38, 37
G0, G1, G2, G3
Logic Inputs. These pins are used to program the gain setting of the front-end amplifiers. If all four
pins are tied low, the PD0 pin acts as a data input pin, DIN, and all programming is made via the
control register (see Table 6).
27
VDRIVE
Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what
voltage the interface operates, including the comparator outputs. This pin should be decoupled to
DGND.
44, 17
CA_CB_GND,
CC_CD_GND
Comparator Ground. This is the ground reference point for all comparator circuitry on the AD7262/
AD7262-5. Both the CA_CB_GND pin and the CC_CD_GND pin should connect to the GND plane of a
system and can be tied to AGND. The DGND, AGND, CA_CB_GND, and CC_CD_GND voltages should
ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
24
REFSEL
Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the on-
chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is
tied to GND, an external reference can be supplied to the AD7262/AD7262-5 through the VREFA
and/or VREFB pin.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
AD7264BCPZ IC ADC 14BIT 2CH 1MSPS 48LFCSP
AD7265BSUZ-REEL7 IC ADC 12BIT 3CHAN 1MSPS 32TQFP
AD7266BSUZ IC ADC 12BIT 3CH 2MSPS 32-TQFP
AD7274BRM IC ADC 12BIT 3MSPS HS LP 8MSOP
AD7276BRM IC ADC 12BIT 3MSPS HS LP 8MSOP
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
AD7262BSTZ-5 鍔熻兘鎻忚堪:IC ADC 2CH 12BIT PGA/COM 48LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞夋彌鍣� 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞夋彌鍣ㄦ暩(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔�锛屽柈妤�
AD7262BSTZ-5-RL7 鍔熻兘鎻忚堪:IC ADC 12BIT W/PGA&COM 48-LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞夋彌鍣� 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞夋彌鍣ㄦ暩(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔�锛屽柈妤�
AD7262BSTZ-RL7 鍔熻兘鎻忚堪:IC ADC 12BIT W/PGA&COM 48-LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞夋彌鍣� 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞夋彌鍣ㄦ暩(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔紝鍠サ
AD7264 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators
AD7264BCPZ 鍔熻兘鎻忚堪:IC ADC 14BIT 2CH 1MSPS 48LFCSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞夋彌鍣� 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:300k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞夋彌鍣ㄦ暩(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:75mW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:24-SOIC 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔�锛屽柈妤�锛�1 鍊嬪柈绔�锛岄洐妤�
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京銆�

閲囪臣闇€姹�

(鑻ュ彧閲囪臣涓€姊濆瀷铏�锛屽～瀵竴琛屽嵆鍙�)

鐧�(f膩)甯冩垚鍔燂紒鎮ㄥ彲浠ョ辜绾�(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫插叆鎴戠殑鍚庤嚭锛屾煡鐪嬪牨鍍�

鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩笺€備篃鍙互閫插叆鎴戠殑鍚庤嚭锛屾煡鐪嬪牨鍍�

*鍨嬭櫉 *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉 灏佽
娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

*
*
*
    • 鎴�
    • 閲囪喘
    • 鎼滅储
    • 浼氬憳