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參數(shù)資料
| 型號： | AD7233 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Serial Mini-DIP DACPORT(12位電壓輸出D/A轉(zhuǎn)換器) |
| 中文描述： | 12位串行微型DIP DACPORT（12位電壓輸出的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 128K |
| 代理商： | AD7233 |
AD7233
REV. 0
–7–
MICROPROCE SSOR INT E RFACING
Microprocessor interfacing to the AD7233 is via a serial bus
which uses standard protocol compatible with DSP processors
and microcontrollers. T he communications channel requires a
three-wire interface consisting of a clock signal, a data signal and
a synchronization signal. T he AD7233 requires a 16-bit data
word with data valid on the falling edge of SCLK . For all of the
interfaces, the DAC update may be done automatically when all
the data is clocked in or it may done under control of
LDAC
.
Figures 5 to 8 show the AD7233 configured for interfacing to a
number of popular DSP processors and microcontrollers.
AD7233–ADSP-2101/ADSP-2102 Interface
Figure 5 shows a serial interface between the AD7233 and the
ADSP-2101/ADSP-2102 DSP processor. T he ADSP-2101/
ADSP-2102 contains two serial ports, and either port may be
used in the interface. T he data transfer is initiated by
TFS
going
low. Data from the ADSP-2101/ADSP-2102 is clocked into the
AD7233 on the falling edge of SCLK . When the data transfer is
complete
TFS
is taken high. In the interface shown the DAC is
updated using an external timer which generates an
LDAC
pulse. T his could also be done using a control or decoded ad-
dress line from the processor. Alternatively, the
LDAC
input
could be hardwired low, and in this case the automatic update
mode is selected whereby the DAC update takes place automati-
cally on the 16th falling edge of SCLK .
TIMER
LDAC
ADSP-2101/
ADSP-2102*
SDIN
SCLK
* ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
SCLK
DT
AD7233*
TFS
Figure 5. AD7233 to ADSP-2101/ADSP-2102 Interface
AD7233-DSP56000 Interface
A serial interface between the AD7233 and the DSP56000 is
shown in Figure 6. T he DSP56000 is configured for Normal
Mode Asynchronous operation with Gated Clock. It is also set
up for a 16-bit word with SCK and SC2 as outputs and the FSL
control bit set to a 0. SCK is internally generated on the
DSP56000 and applied to the AD7233 SCLK input. Data from
the DSP56000 is valid on the falling edge of SCK . T he SC2
output provides the framing pulse for valid data. T his line must
be inverted before being applied to the
SYNC
input of the
AD7233.
T he
LDAC
input of the AD7233 is connected to GND so the
update of the DAC latch takes place automatically on the 16th
falling edge of SCLK . An external timer could also be used as in
the previous interface if an external update is required.
LDAC
DSP56000
SCLK
SDIN
SCK
STD
* ADDITIONAL PINS OMITTED FOR CLARITY
AD7233*
SC2
SYNC
Figure 6. AD7233 to DSP56000 Interface
AD7233–87C51 Interface
A serial interface between the AD7233 and the 87C51 micro-
controller is shown in Figure 7. T X D of the 87C51 drives
SCLK of the AD7233 while RX D drives the serial data line of
the part. T he
SYNC
signal is derived from the port line P3.3.
T he 87C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. T herefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
the don’t care bits are the first to be transmitted to the AD7233
and the last bit to be sent is the LSB of the word to be loaded to
the AD7233. When data is to be transmitted to the part, P3.3 is
taken low. Data on RX D is valid on the falling edge of T X D.
T he 87C51 transmits its serial data in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. T o load data
to the AD7233, P3.3 is kept low after the first eight bits are
transferred and a second byte of data is then transferred serially
to the AD7233. When the second serial transfer is complete, the
P3.3 line is taken high.
Figure 7 shows the
LDAC
input of the AD7233 hardwired low.
As a result, the DAC latch and the analog output will be up-
dated on the sixteenth falling edge of T X D after the
SYNC
sig-
nal for the DAC has gone low. Alternatively, the scheme used in
previous interfaces, whereby the
LDAC
input is driven from a
timer, can be used.
LDAC
87C51*
SDIN
TXD
* ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
SCLK
RXD
AD7233*
P3.3
Figure 7. AD7233 to 87C51 Interface
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| AD7233AN | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 12-bit 8-Pin PDIP Tube 制造商:Rochester Electronics LLC 功能描述:SERIAL 12-BIT DACPORT IC - Bulk 制造商:Analog Devices 功能描述:D/A Converter (D-A) |
| AD7233ANZ | 功能描述:IC DAC 12BIT LC2MOS SRL 8-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:DACPORT® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD7233ANZ | 制造商:Analog Devices 功能描述:D/A Converter (D-A) IC |
| AD7233BN | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 12-bit 8-Pin PDIP Tube 制造商:Analog Devices 功能描述:SEMICONDUCTORSLINEAR |
| AD7233BNZ | 功能描述:IC DAC 12BIT SRL W/AMP 8PDIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:DACPORT® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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