參數(shù)資料
型號(hào): AD7233
廠商: Analog Devices, Inc.
英文描述: 12-Bit Serial Mini-DIP DACPORT(12位電壓輸出D/A轉(zhuǎn)換器)
中文描述: 12位串行微型DIP DACPORT(12位電壓輸出的D / A轉(zhuǎn)換器)
文件頁數(shù): 2/8頁
文件大?。?/td> 128K
代理商: AD7233
REV. 0
–2–
AD7233–SPECIFICATIONS
1
(V
DD
= +12 V to +15 V,
2
V
SS
= –12 V to –15 V,
2
GND = 0 V, R
L
= 2 k
V
,
C
L
= 100 pF to GND. All specifications T
MN
to T
MAX
unless otherwse noted.)
Parameter
A
B
Units
T est Conditions/Comments
ST AT IC PERFORMANCE
Resolution
Relative Accuracy
3
Differential Nonlinearity
3
Bipolar Zero Error
3
Full-Scale Error
3
Full-Scale T emperature Coefficient
±
30
12
±
1
±
0.9
±
6
±
8
12
±
1/2
±
0.9
±
6
±
8
±
30
Bits
LSB max
LSB max
LSB max
LSB max
ppm of FSR/
°
C typ
Guaranteed Monotonic
DAC Latch Contents 0000 0000 0000
DIGIT AL INPUT S
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
IN
Input Capacitance
4
2.4
0.8
2.4
0.8
V min
V max
±
1
8
±
1
8
μ
A max
pF max
V
IN
= 0 V to V
DD
ANALOG OUT PUT S
Output Voltage Range
DC Output Impedance
±
5
0.5
±
5
0.5
V
typ
AC CHARACT ERIST ICS
4
Voltage Output Settling T ime
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
3
Digital Feedthrough
3
Settling T ime to Within
±
1/2 LSB of Final Value
T ypically 3
μ
s; DAC Latch 100. . .000 to 011. . .111
T ypically 5
μ
s; DAC Latch 011. . .111 to 100. . .000
DAC Latch Contents T oggled Between All 0s and all 1s
LDAC
= High
10
10
30
10
10
10
30
10
μ
s max
μ
s max
nV secs typ
nV secs typ
POWER REQUIREMENT S
V
DD
Range
V
SS
Range
I
DD
I
SS
+10.8/+16.5
–10.8/–16.5
10
4
+11.4/+15.75 V min/V max
–11.4/–15.75
10
4
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Output Unloaded; T ypically 7 mA
Output Unloaded; T ypically 2 mA
V min/V max
mA max
mA max
NOT ES
1
T emperature Ranges are as follows: A, B Versions: –40
°
C to +85
°
C.
2
Power Supply T olerance: A Version:
±
10%; B Version:
±
5%.
3
See T erminology.
4
Sample tested @ +25
°
C to ensure compliance.
Specifications subject to change without notice.
TIMNGCHARACTERISTICS
1, 2
Limit at +25
8
C
(All Versions)
Limit at T
MIN
, T
MAX
(All Versions)
Parameter
Units
Conditions/Comments
t
13
t
2
t
3
t
4
t
5
t
6
t
7
t
8
200
50
120
10
100
0
50
0
200
50
190
10
100
0
50
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle T ime
SYNC
to SCLK Falling Edge Setup T ime
SYNC
to SCLK Hold T ime
Data Setup T ime
Data Hold T ime
SYNC
High to
LDAC
Low
LDAC
Pulse Width
LDAC
High to
SYNC
Low
NOT ES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
SCLK Mark/Space Ratio range is 40/60 to 60/40.
(V
DD
= +10.8 V to +16.5 V, V
SS
= –10.8 V to –16.5 V, GND = OV, R
L
= 2 k
V
,
C
L
= 100 pF. All Specifications T
MN
to T
MAX
unless otherwse noted.)
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