AVDD = 4.75 V to 5.25 V, DV<" />
參數(shù)資料
型號(hào)： AD7195BCPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 43/45頁
文件大小： 0K
描述： IC AFE 24BIT 4.8K 32LFSP
設(shè)計(jì)資源： Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155)
標(biāo)準(zhǔn)包裝： 5,000
位數(shù)： 24
通道數(shù)： 4
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 2.7 V ~ 5.25 V
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 帶卷 (TR)
AD7195
Rev. 0 | Page 6 of 44
TIMING CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless
otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX (B Version)
Unit
Conditions/Comments1, 2
READ AND WRITE OPERATIONS
t3
100
ns min
SCLK high pulse width
t4
100
ns min
SCLK low pulse width
READ OPERATION
t1
0
ns min
CS falling edge to DOUT/RDY active time
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
t23
0
ns min
SCLK active edge to data valid delay4
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
10
ns min
Bus relinquish time after CS inactive edge
80
ns max
t6
0
ns min
SCLK inactive edge to CS inactive edge
t7
10
ns min
SCLK inactive edge to DOUT/RDY high
WRITE OPERATION
t8
0
ns min
CS falling edge to SCLK active edge setup time4
t9
30
ns min
Data valid to SCLK edge setup time
t10
25
ns min
Data valid to SCLK edge hold time
t11
0
ns min
CS rising edge to SCLK edge hold time
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2 See Figure 3 and Figure 4.
3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 The SCLK active edge is the falling edge of SCLK.
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
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AD7195BCPZ-RL7 功能描述:IC AFE 24BIT 4.8K 32LFSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR)
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