參數(shù)資料
型號： AD7195BCPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 35/45頁
文件大小： 0K
描述： IC AFE 24BIT 4.8K 32LFSP
設計資源： Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155)
標準包裝： 5,000
位數(shù)： 24
通道數(shù)： 4
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 2.7 V ~ 5.25 V
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應商設備封裝： 32-LFCSP-WQ（5x5）
包裝： 帶卷 (TR)
AD7195
Rev. 0 | Page 39 of 44
When a channel change occurs, the modulator and filter reset.
The complete settling time is required to generate the first
conversion after the channel change. Subsequent conversions
on this channel occur at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
CH B
0
87
71
-0
52
Figure 41. Channel Change (Sinc4 Chop Enabled)
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in
analog input; therefore, it continues to output conversions at
the programmed output data rate. However, it is at least two
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is
processing a conversion, the ADC takes three conversions after
the step change to generate a fully settled result.
1/
fADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
0
877
1-
0
53
Figure 42. Asynchronous Step Change in Analog Input (Sinc4 Chop Enabled)
The cutoff frequency f3dB is equal to
f3dB = 0.24 × fADC
50 Hz/60 Hz Rejection (Sinc4 Chop Enabled)
When FS[9:0] is set to 96 and chopping is enabled, the output
data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The
filter response shown in Figure 43 is obtained. The chopping
introduces notches at odd integer multiples of fADC/2. The
notches due to the sinc filter in addition to the notches intro-
duced by the chopping mean that simultaneous 50 Hz and
60 Hz rejection is achieved for an output data rate of 12.5 Hz.
The rejection at 50 Hz/60 Hz ± 1 Hz is typically 63 dB,
assuming a stable master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
F
IL
T
E
R
GA
IN
(
d
B
)
0
87
71
-05
4
Figure 43. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled)
The 50 Hz/60 Hz rejection can be improved by setting the
REJ60 bit in the mode register to 1. With FS[9:0] set to 96
and REJ60 set to 1, the filter response shown Figure 44
is achieved. The output data rate is unchanged but the 50 Hz/
60 Hz (± 1 Hz) rejection is increased to 83 dB typically.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
F
IL
T
E
R
GA
IN
(d
B
)
08
77
1-
0
55
Figure 44. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1)
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