VDD = 2.7 V to 3.6 V; GND = 0" />
參數(shù)資料
型號: AD7152BRMZ
廠商: Analog Devices Inc
文件頁數(shù): 20/24頁
文件大?。?/td> 0K
描述: IC CDC 12BIT 2/4CH 10MSOP
特色產(chǎn)品: AD715x Series Capacitance-to-Digital Converters & Evaluation Board
標(biāo)準(zhǔn)包裝: 50
類型: 電容數(shù)字轉(zhuǎn)換器
分辨率(位): 12 b
數(shù)據(jù)接口: 串行
電壓電源: 單電源
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
配用: EVAL-AD7152EBZ-ND - BOARD EVAL AD7152
AD7152/AD7153
Rev. 0 | Page 5 of 24
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; 40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SERIAL INTERFACE1, 2
SCL Frequency
0
400
kHz
SCL High Pulse Width, tHIGH
0.6
μs
SCL Low Pulse Width, tLOW
1.3
μs
SCL, SDA Rise Time, tR
0.3
μs
SCL, SDA Fall Time, tF
0.3
μs
Hold Time (Start Condition), tHD;STA
0.6
μs
After this period, the first clock is generated.
Set-Up Time (Start Condition), tSU;STA
0.6
μs
Relevant for repeated start condition.
Data Set-Up Time, tSU;DAT
0.1
μs
Setup Time (Stop Condition), tSU;STO
0.6
μs
Data Hold Time, tHD;DAT (Master)
0.01
μs
Bus-Free Time (Between Stop and Start Conditions, tBUF)
1.3
μs
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs;
output load = 10 pF.
P
S
tLOW
tR
tF
tHD;STA
tHD;DAT
tSU;DAT
tSU;STA
tHD;STA
tSU;STO
tHIGH
SCL
PS
SDA
tBUF
07
45
0-
0
03
Figure 3. Serial Interface Timing Diagram
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