參數(shù)資料
型號(hào)： AD7152BRMZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 0K
描述： IC CDC 12BIT 2/4CH 10MSOP
特色產(chǎn)品： AD715x Series Capacitance-to-Digital Converters & Evaluation Board
標(biāo)準(zhǔn)包裝： 50
類型： 電容數(shù)字轉(zhuǎn)換器
分辨率（位）： 12 b
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 2.7 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 781 (CN2011-ZH PDF)
配用： EVAL-AD7152EBZ-ND - BOARD EVAL AD7152
AD7152/AD7153
Rev. 0 | Page 20 of 24
DIFFERENTIAL CAPACITIVE INPUT
When configured for differential mode (the CAPDIFF bit in the
Channel 1 Setup or Channel 2 Setup registers is set to 1), the
CDC measures the difference between positive and negative
capacitance input.
Each of the two input capacitances, CX and CY, between the
EXC and CIN pins must be less than 2 pF (without using the
CAPDACs) or must be less than 9 pF and balanced by the
CAPDACs. Balancing by the CAPDACs means that both
CX CAPDAC(+) and CY CAPDAC() are less than 2 pF.
If the unbalanced capacitance between the EXC and CIN pins
is higher than 2 pF, the CDC introduces a gain error, an offset
error, and nonlinearity error (see Figure 32, Figure 33, and
0x0000 ... 0xFFF0
DATA
CAPDIFF = 1
±2pF
CDC
EXC
CIN(+)
CIN(–)
CX
0pF TO 4pF
CY
0pF TO 4pF
CAPDAC(+)
OFF
CAPDAC(–)
OFF
07
45
0-
0
20
Figure 32. CDC Differential Input Mode
0x0000 ... 0xFFF0
DATA
CAPDIFF = 1
±2pF
CDC
EXC
CIN(+)
CIN(–)
CX
4pF TO 6pF
(5 ± 1pF)
CY
4pF TO 6pF
(5 ± 1pF)
CAPDAC(+)
5pF
CAPDAC(–)
5pF
07
45
0-
0
21
Figure 33. Using CAPDAC in Differential Mode
0x0000 ... 0xFFF0
DATA
CAPDIFF = 1
±2pF
CDC
EXC
CIN(+)
CIN(–)
CX
3pF TO 7pF
(5 ± 2pF)
CY
5pF
CAPDAC(+)
5pF
CAPDAC(–)
5pF
07
45
0-
1
21
Figure 34. Using CAPDAC in Differential Mode
PARASITIC CAPACITANCE TO GROUND
DATA
CDC
EXC
CGND1
CIN
CGND2
CX
07
45
0-
0
1
2
Figure 35. Parasitic Capacitance to Ground
The CDC architecture used in the AD7152/AD7153 measures
CX connected between the EXC pin and the CIN pin. In theory,
any capacitance, CGND, to ground should not affect the CDC
result (see Figure 35).
The practical implementation of the circuitry in the chip
implies certain limits and the result is gradually affected by
capacitance to ground. See the allowed capacitance to GND
in the Specifications table and, Figure 9 through Figure 12.
PARASITIC RESISTANCE TO GROUND
DATA
CDC
EXC
RGND1
CIN
RGND2
CX
07
45
0-
0
13
Figure 36. Parasitic Resistance to Ground
The CDC result can be affected by a leakage current from
the CX to ground; therefore, the CX should be isolated from
the ground. The influence of the leakage current varies with
the power supply voltage (see Figure 36).
A higher leakage current to ground results in a gain error,
an offset error, and a nonlinearity error (see Figure 13 and
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