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參數(shù)資料
| 型號： | AD6816 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片) |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 483K |
| 代理商： | AD6816 |
AD6816
–5–
REV. A
DEFINITION OF TERMS
Maximum, Minimum and Typical Specifications
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribu-
tion. This procedure is intended to tolerate production varia-
tions: if the mean shifts by 1.5 standard deviations, the remaining
4.5 standard deviations still provide a failure rate of only 3.4
parts per million. For all tested parameters, the test limits are
guardbanded to account for tester variation to guarantee that
no device is shipped outside of data sheet specifications.
Signal Detect: Response Time
Response time is the delay between removal of a dc-coupled input
signal (at RX & RXN) and indication of loss of signal (LOS) at
SDOUT.
Clock Recovery PLL: Static Phase Error
This is the steady-state phase difference, in degrees, between
the recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error and IC input and output signals pro-
hibit direct measurement of static phase error.
Data Transition Density,
r
This is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods.
ρ
is the ra-
tio (0 <
ρ
< 1) of data transitions to bit periods. The 2
23
–1 PRN
input data pattern has
ρ
= 1/2.
PLL Jitter
This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms or
Unit Intervals (UI).
Output Jitter
This is the jitter on the clock recovery PLL or frequency synthe-
sizer PLL output clock, in degrees rms, due to a specific pattern
or some pseudo random input data sequence (PRN sequence).
Jitter Transfer
The clock recovery PLL and frequency synthesizer PLL both
exhibit a low-pass filter response to jitter applied to their
respective inputs.
Bandwidth
This describes the frequency at which the clock recovery PLL
or frequency synthesizer PLL attenuate sinusoidal input jitter
by 3 dB.
Frequency Synthesizer PLL: Duty Cycle Tolerance
The frequency synthesizer PLL exhibits a duty cycle tolerance
that is measured by applying an input signal (nominal input
frequency) with a known duty cycle imbalance, and then mea-
suring the output frequency and jitter.
Time Constant
The Frequency Synthesizer PLL time constant (800 ns =
1/bandwidth) determines the output frequency drift after
switching the reference frequency input. The time constant
works to smooth the output frequency response to change in
reference input guaranteeing no runt pulses at the output.
Crystal Oscillator
The AD6816 integrated oscillator circuit is specified to provide
a 19.44 MHz output frequency with
±
100 ppm frequency accu-
racy using a 19.44 MHz
±
50 ppm series mode crystal with
series resistance less than 40
.
A series mode crystal oscillator is used instead of the more com-
mon parallel mode circuit. The primary advantage of the series
mode oscillator is that shunt capacitance has no effect since the
crystal presents a low impedance at resonance. All the accuracy
inherent in the crystal can be achieved by the series mode cir-
cuit. In contrast, the parallel mode circuit requires a trimmer
capacitor shunt to the crystal to compensate stray capacitances.
In addition, these stray and trim capacitances must be stable
over temperature for high accuracy. Crystal vendors easily sup-
ply either type of crystal. It is necessary to specify that a series
mode crystal is needed.
Oscillator Circuit: Duty Cycle
Duty cycle is calculated as (100
×
on time)/period, where on
time equals the time the clock signal is greater than the mid-
point between its “0” level and its “1” level.
Line Driver Differential Input (Refer to Figure 2)
The line driver is specified to provide output current variation
less than 1% with a 3 V input common-mode signal and a dif-
ferential input signal between 150 mV and 1 V p-p.
AD6816
LINE DRIVER
DRIVEIN
DRIVEINN
SCOPE
V
CM
V
CM
= 3V
DIFFERENTIAL
INPUT = 150mV p–p
MINIMUM
32
33
Figure 2. Line Driver Differential Input (Single-Ended
Measurement Shown)
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