參數(shù)資料
型號(hào)： AD6816
廠商： Analog Devices, Inc.
英文描述： Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡(luò)接口與#5類(lèi)非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片)
文件頁(yè)數(shù)： 18/20頁(yè)
文件大小： 483K
代理商： AD6816
AD6816
–18–
REV. A
5 V PECL to 3.3 V PECL Interface Analysis
The following three equations must be satisfied for this inter-
face (in the following example: R
H
= Resistor connected to
PECL 5 V, R
M
= Resistor connected between termination line
and destination pin, and R
L
= Resistor connected to ground):
1. Termination Impedance must match trace impedance:
Termination impedance
= (
R
H
×
(
R
M
+
R
L
))/
(
R
H
+
R
M
+
R
L
) = 50
.
2. Resistors need to provide the correct voltage levels:
(
V
SOURCE
–
V
TERM_DESTINATION
)/
R
M
=
V
TERM_DESTINATION
)/
R
L
,
where
V
SOURCE
= 3.67 V (PECL 5 V midpoint) and
V
TERM_DESTINATION
= 2.0 V PECL 3.3 V midpoint).
3. Desired driver current of 25 mA:
I
DRIVE
= [(4 –
V
DEST_HIGH
)/
R
M
] – [(5–4)/R
H
],
where
V
DEST_HIGH
= (4
×
R
L
)/(R
M
+ R
L
) and
I
DRIVE
= 0.025.
The midpoints are used to ensure that the waveforms are cen-
tered at the critical levels. The waveform is attenuated at the
destination because of the voltage divider. Rounding the resis-
tor values to the nearest standard 5% resistors results in the cir-
cuit of Figure 30. A 3.2 V to 4.0 V input swing into this circuit
creates an output swing between 1.8 V and 2.2 V.
3.3 V PECL to 5 V PECL Interface Analysis
The common-mode rejection area of the AD6816 line driver
input requires the input signal voltage swing to be above 2.6 V.
This is lower than standard PECL and helps simplify the termi-
nation resistor network (less driver current is required). In the
following example: R
H
= Resistor connected to PECL 5 V, R
M
= Resistor connected between termination line and destination
pin, and R
L
= Resistor connected to ground). The following
three equations need to be satisfied for this interface:
1. The voltage swings need to be centered at the correct volt-
age levels:
(5 –
V
MID_DESTINATION
)/
R
H
= (
V
MID_DESTINATION
–
V
MID_SOURCE
)/R
M
,
where
V
MID_DESTINATION
= 3.0 V and
V
MID_SOURCE
= 2.0 V.
2. Termination Impedance must match trace impedance:
Termination impedance
=
(R
L
×
(R
M
+ R
H
))/
(R
H
+ R
M
+ R
L
) =
50
.
3. The voltage for the driver should be within 5% of 1.7 V for
the proper swing:
V
SOURCE
= (5
×
R
L
)/(R
H
+
R
M
+
R
L
),
where
V
SOURCE
= 1.7 V.
Using these equations, and rounding the resistor values to the
nearest standard 5% resistors, results in the circuit of Figure 31.
This circuit will result in a source voltage swing between 1.66 V
and 2.4 V and a destination voltage swing between 2.79 V and
3.28 V. This exceeds the minimum required voltage swing, with
plenty of margin.
4. Also, the current required by the driver must be less than
17 mA:
I
DRIVE
= (2.4/
R
L
) – [(5 – V
TERM_DESTINATION_HIGH
)/R
H
In this case, the current of the driver is 15 mA.
Example 2: 155 Mbps NIC (Fiber or UTP#5) Using AD6816
& Siemens* ATM Chip Set
The following circuit implementation example shows how to
implement a 155 Mbps ATM Network Interface Card (NIC) to
Fiber Optics or to Category #5 Unshielded Twisted Pair cable
(UTP#5) using the AD6816 with the Siemens PXB 4240 Syn-
chronous Digital Hierarchy Transceiver IC (SDHT) and the
PXB 4110 Segmentation and Reassembly Element IC (SARE).
Contact Siemens Semiconductor, Dusseldorf, Germany, (49)
203 74201 45 for information on the NIC implementation or
PXB 4240/PXB 4110 chipset beyond the information provided
below.
AD6816 Interface to Fiber or to UTP#5
The NIC is designed to interface to either Fiber (via a 1
×
9
Fiber Optic Transceiver) or to UTP#5 (via transformer assem-
bly and RJ45 connector). The unused interface is disconnected
by jumpers.
AD6816 Interface to Siemens SDHT
The AD6816 delivers both recovered clock (associated with the
receive data) and transmit clock to the SDHT. The AD6816
recovers the receive clock from the data coming in via the fiber
or the UTP#5 and generates the local clock from a 19.44 MHz
quartz. The AD6816 provides the ability to create the local
155 MHz clock (system clock) from either the 19.44 MHz
crystal, an 19.44 MHz PECL- or TTL-level signal, or the
155 MHz recovered clock.
The AD6816 high speed signal inputs and outputs operate at
PECL levels. The Siemens SDHT is a 3.3 V CMOS device that
uses IEEE LVDS levels (Low Voltage Differential Signal) for its
high speed signal inputs and outputs. Refer to the paragraphs
below and to Figures 33 and 34 for the description of the inter-
face between the AD6816 and the Siemens SDHT IC.
SDHT/SARE/PCI Bus Interfaces
Interfacing to the PCI bus does not require any external compo-
nents. Nor do the two UTOPIA interfaces between SARE and
SDHT. SARE is master and drives the ATMCLK. The connec-
tion of the SDHT to the SARE’s Local Bus Interface needs a
piece of glue logic to adapt bus cycles.
*All trademarks are properties of their respective holders.
相關(guān)PDF資料
PDF描述
AD693(中文) Loop-Powered 4-20 mA Sensor Transmitter(環(huán)路供電,4-20mA傳感器變送器)
AD7010ARS MIL-spec connector accessory
AD7010 CMOS JDC DQPSK Baseband Transmit Port(CMOS 基帶傳輸口)
AD7011 CMOS, ADC p/4 DQPSK Baseband Transmit Port
AD7011ARS MB 4C 4#12 PIN RECP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6816KST 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
AD681AQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sample/Track-and-Hold Amplifier
AD681SQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sample/Track-and-Hold Amplifier
AD682AN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sample/Track-and-Hold Amplifier
AD682JN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sample/Track-and-Hold Amplifier
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*