- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375235 > AD6816 (Analog Devices, Inc.) Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片) PDF資料下載
參數(shù)資料
| 型號： | AD6816 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片) |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 483K |
| 代理商： | AD6816 |
AD6816
–4–
REV. A
(continued from page 1)
phase. The two loops work in harmony with each other, requir-
ing no control signals for enabling or disabling. Shorting the
clock recovery and data retiming PLL damping factor capacitor,
C
CR
, brings the recovered clock output signal to the clock recov-
ery VCO center frequency.
The crystal oscillator circuit provides an accurate 19.44 MHz
output with a series mode, 19.44 MHz crystal. This circuit
requires no capacitive tuning and can provide a 19.44 MHz,
±
100 ppm output, capable of driving up to five TTL gates or
50 pF load capacitance.
The frequency synthesizer processes either a 19.44 MHz or a
9.72 MHz input signal at the FREF, ECLFREF/ECLFREFN
pins, or the 19.44 MHz byte clock derived from the 155.52 MHz
RXCLKOUT & RXCLKOUTN signal. The RXCLKSEL sig-
nal determines whether or not the derived byte clock is used by
the frequency synthesizer. When the RXCLKSEL signal is high,
the frequency synthesizer processes the derived byte clock.
When the RXCLKSEL signal is left unconnected, or held low,
the frequency synthesizer processes the reference signal at the
FREFIN or ECLFREFIN/ECLFREFINN pins (refer to Table
II). Having the frequency synthesizer loop process either the de-
rived byte clock or a reference eliminates runt pulses that may
occur when switching between two 155.52 MHz bit clocks.
The synthesizer can be configured to accept an external fre-
quency reference in either TTL/CMOS format or in PECL for-
mat. This selection is made by sensing the common-mode
voltage at Pins 23 and 24. If valid PECL levels are present at
Pins 23 and 24, this signal is used as the frequency reference
and any signal present at Pin 25 is ignored. If Pins 23 and 24
are connected to ground (VDN1, Pin 15), the TTL/CMOS
input (Pin 25) is enabled and used as the frequency reference
for the synthesizer.
The AD6816 is packaged in a 44-pin Thin Quad Flatpack
(TQFP), having lead frame dimensions 0.55"
×
0.55".
PIN DESCRIPTION
Pin
No.
Mnemonic
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
SDOUT
VAN1
CEQ1
CEQ2
CCR1
CCR2
VAP1
VDP4
VDN4
RXCLKOUT
RXCLKOUTN
VDPECL1
RXDATAOUT
RXDATAOUTN
VDN1
VDPECL2
TXCLKOUT
TXCLKOUTN
VDP1
CFS1
CFS2
VAP2
ECLFREFINN
ECLFREFIN
FREFIN
OSCOUT
VDP2
VDN2
XTALIN1
XTALIN2
VAN2
DRIVEINN
DRIVEIN
VDN3
TXAMPSET
VDP3
TX
TXN
DRVROFF
RXCLKSEL
LBSELECT
DRBYPASS
RX
RXN
Signal Detect Output
Analog Ground—Clock Recovery and Equalizer
Equalizer Loop Filter Capacitor
Equalizer Loop Filter Capacitor
Clock Recovery Loop Damping Capacitor
Clock Recovery Loop Damping Capacitor
Analog Supply—Clock Recovery and Equalizer
Digital Supply—Clock Recovery Logic and Mux
Digital Ground—Clock Recovery Logic and Mux
Differential Recovered Clock Output
Differential Recovered Clock Output
Digital Supply—Clock and Data Output Drivers
Differential Recovered Data Output
Differential Recovered Data Output
Digital Ground—Synthesizer Logic
Digital Supply—Synthesizer Driver
Differential Synthesized Clock Output
Differential Synthesized Clock Output
Digital Supply—Synthesizer Logic
Synthesizer Loop Filter Capacitor
Synthesizer Loop Filter Capacitor
Analog Supply—Synthesizer & Oscillator
Differential ECL Input to Synthesizer
Differential ECL Input to Synthesizer
CMOS/TTL Input to Synthesizer
Crystal Oscillator CMOS/TTL Output
Digital Supply—Oscillator Output
Digital Ground—Oscillator Output
Crystal Connection
Crystal Connection
Analog Ground—Synthesizer and Oscillator
Line Driver Differential ECL Input
Line Driver Differential ECL Input
Digital Ground—Line Driver
Line Driver Output Current Control
Digital Supply—Line Driver
Line Driver Collector Output
Line Driver Collector Output
Line Driver Disable (CMOS/TTL)
Synthesizer Frequency Reference Select
Loop-Back Select
Data Retiming Bypass
Differential Equalizer Input
Differential Equalizer Input
相關PDF資料 |
PDF描述 |
|---|---|
| AD693(中文) | Loop-Powered 4-20 mA Sensor Transmitter(環(huán)路供電,4-20mA傳感器變送器) |
| AD7010ARS | MIL-spec connector accessory |
| AD7010 | CMOS JDC DQPSK Baseband Transmit Port(CMOS 基帶傳輸口) |
| AD7011 | CMOS, ADC p/4 DQPSK Baseband Transmit Port |
| AD7011ARS | MB 4C 4#12 PIN RECP |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6816KST | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD681AQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sample/Track-and-Hold Amplifier |
| AD681SQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sample/Track-and-Hold Amplifier |
| AD682AN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sample/Track-and-Hold Amplifier |
| AD682JN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sample/Track-and-Hold Amplifier |
發(fā)布緊急采購，3分鐘左右您將得到回復。