參數(shù)資料
型號(hào): AD6654BBC
廠商: Analog Devices Inc
文件頁數(shù): 83/88頁
文件大?。?/td> 0K
描述: IC ADC 14BIT W/6CH RSP 256CSPBGA
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 92.16M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.5W
電壓電源: 模擬和數(shù)字
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA,CSPBGA
供應(yīng)商設(shè)備封裝: 256-CSPBGA(17x17)
包裝: 托盤
輸入數(shù)目和類型: 1 個(gè)差分,單極
AD6654
Rev. 0 | Page 84 of 88
AGC0, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC0. Note that AGC0 might be bypassed, and
that AGC0 here is representative of the datapath only.
AGC0, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC0. Note that AGC0 might be bypassed,
and that AGC0 here is representative of the datapath only.
AGC1, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC1. Note that AGC1 might be bypassed and
that AGC1 here is representative of the datapath only.
AGC1, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC1. Note that AGC1 might be bypassed
and that AGC1 here is representative of the datapath only.
AGC2, I Output <15:0:
This read-only register provides the latest in-phase output
sample from AGC2. Note that AGC2 might be bypassed and
that AGC2 here is representative of the datapath only.
AGC2, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC2. Note that AGC2 might be bypassed
and that AGC2 here is representative of the datapath only.
AGC3, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC3. Note that AGC3 might be bypassed and
that AGC3 here is representative of the datapath only.
AGC3, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC3. Note that AGC3 might be bypassed
and that AGC3 here is representative of the datapath only.
AGC4, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC4. Note that AGC4 might be bypassed and
that AGC4 here is representative of the datapath only.
AGC4, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC4. Note that AGC4 might be bypassed
and that AGC4 here is representative of the datapath only.
AGC5, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC5. Note that AGC5 might be bypassed and
that AGC5 here is representative of the datapath only.
AGC5, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC5. Note that AGC5 might be bypassed
and that AGC5 here is representative of the datapath only.
AGC0, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC0. This register is updated only when AGC0 is
enabled and operating.
AGC1, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC1. This register is updated only when AGC1is
enabled and operating.
AGC2, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC2. This register is updated only when AGC2 is
enabled and operating.
AGC3, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC3. This register is updated only when AGC3 is
enabled and operating.
AGC4, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC4. This register is updated only when AGC4 is
enabled and operating.
AGC5, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC5. This register is updated only when AGC5 is
enabled and operating.
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