參數(shù)資料
型號: AD6654BBC
廠商: Analog Devices Inc
文件頁數(shù): 2/88頁
文件大?。?/td> 0K
描述: IC ADC 14BIT W/6CH RSP 256CSPBGA
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 92.16M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.5W
電壓電源: 模擬和數(shù)字
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA,CSPBGA
供應(yīng)商設(shè)備封裝: 256-CSPBGA(17x17)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
AD6654
Rev. 0 | Page 10 of 88
MICROPORT TIMING CHARACTERISTICS
Table 8.
Temp
Test Level
Min
Typ
Max
Unit
MICROPORT CLOCK TIMING REQUIREMENTS
tCPUCLK
CPUCLK Period
Full
IV
10.0
ns
tCPUCLKL
CPUCLK Low Time
Full
IV
1.53
0.5 × tCPUCLK
ns
tCPUCLKH
CPUCLK High Time
Full
IV
1.70
0.5 × tCPUCLK
ns
INM MODE WRITE TIMING (MODE = 0)
tSC
Control3 to
↑CPUCLK Setup Time
Full
IV
0.80
ns
tHC
Control3 to
↑CPUCLK Hold Time
Full
IV
0.09
ns
tSAM
Address/Data to
↑CPUCLK Setup Time
Full
IV
0.76
ns
tHAM
Address/Data to
↑CPUCLK Hold Time
Full
IV
0.20
ns
tDRDY
↑CPUCLK to RDY (DTACK) Delay
Full
IV
3.51
6.72
ns
tACC
Write Access Time
Full
IV
3 × tCPUCLK
9 × tCPUCLK
ns
INM MODE READ TIMING (MODE = 0)
tSC
Control3 to
↑CPUCLK Setup Time
Full
IV
1.00
ns
tHC
Control3 to
↑CPUCLK Hold Time
Full
IV
0.03
ns
tSAM
Address to
↑CPUCLK Setup Time
Full
IV
0.80
ns
tHAM
Address to
↑CPUCLK Hold Time
Full
IV
0.20
ns
tDD
↑CPUCLK to Data Delay
Full
V
5.0
ns
tDRDY
↑CPUCLK to RDY (DTACK) Delay
Full
IV
4.50
6.72
ns
tACC
Read Access Time
Full
IV
3 × tCPUCLK
9 × tCPUCLK
ns
MNM MODE WRITE TIMING (MODE = 1)
tSC
Control3 to
↑CPUCLK Setup Time
Full
IV
1.00
ns
tHC
Control3 to
↑CPUCLK Hold Time
Full
IV
0.00
ns
tSAM
Address/Data to
↑CPUCLK Setup Time
Full
IV
0.00
ns
tHAM
Address/Data to
↑CPUCLK Hold Time
Full
IV
0.57
ns
tDDTACK
↑CPUCLK to DTACK (RDY) Delay
Full
IV
4.10
5.72
ns
tACC
Write Access Time
Full
IV
3 × tCPUCLK
9 × tCPUCLK
ns
MNM MODE READ TIMING (MODE = 1)
tSC
Control3 to
↑CPUCLK Setup Time
Full
IV
1.00
ns
tHC
Control3 to
↑CPUCLK Hold Time
Full
IV
0.00
ns
tSAM
Address to
↑CPUCLK Setup Time
Full
IV
0.00
ns
tHAM
Address to
↑CPUCLK Hold Time
Full
IV
0.57
ns
tDD
CPUCLK to Data Delay
Full
V
5.0
ns
tDDTACK
↑CPUCLK to DTACK (RDY) Delay
Full
IV
4.20
6.03
ns
tACC
Read Access Time
Full
IV
3 × tCPUCLK
9 × tCPUCLK
ns
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V, and the VDDIO range of 3.0 V to 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
3 Specification pertains to control signals: R/W, (WR), DS, (RD), and CS.
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