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| 型號： | AD6654BBC |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT W/6CH RSP 256CSPBGA |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 92.16M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSPBGA |
| 供應商設備封裝： | 256-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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AD6654
Rev. 0 | Page 35 of 88
If the carrier frequency is 70 MHz and the clock frequency is
80 MHz, then:
125
.
0
80
10
)
,
mod(
=
CLK
CH
f
This, in turn, converts to 0xE000 0000 in the twos complement
32-bit representation.
MIXER
The NCO is accompanied by a mixer. Its operation is similar to
an analog mixer. It performs the down-conversion of real input
signals by using the NCO frequency as a local oscillator. This
mixer performs a real mixer operation (with two multipliers).
The mixer adjusts its operation based on the input signal
provided to each individual channel.
BYPASS
The NCO and the mixer can be individually bypassed in each
channel by writing Logic 1 in the NCO bypass bit in the NCO
control register of the channel under consideration.
CLEAR PHASE ACCUMULATOR ON HOP
When clear, the NCO accumulator bit of the NCO control
register is set (Logic 1), the NCO phase accumulator is cleared
prior to a frequency hop. Refer to the Chip Synchronization
section for details on frequency hopping. This ensures a
consistent phase of the NCO on each hop. The NCO phase
offset is unaffected by this setting and is still in effect. If phase-
continuous hopping is needed, this bit should be cleared (NCO
accumulator is not cleared). The last phase in the NCO phase
register is the initiating point for the new frequency.
PHASE DITHER
The AD6654 provides a phase dither option for improving the
spurious performance of the NCO. Writing Logic 1 in the phase
dither enable bit of the NCO control register of individual
channels enables phase dither. When phase dither is enabled,
random phase is added to the LSBs of the phase accumulator of
the NCO. When phase dither is enabled, spurs due to phase
truncation in the NCO are randomized.
The energy from these spurs is spread into the noise floor and
the spurious free dynamic range is increased at the expense of a
very slight decrease in the SNR. The choice of whether to use
phase dither in a system is ultimately decided by the system
goals. If lower spurs are desired at the expense of a slightly
raised noise floor, phase dither should be employed. If a low
noise floor is desired and higher spurs can be tolerated or
filtered by subsequent stages, then phase dither is not needed.
AMPLITUDE DITHER
Amplitude dither can be used to improve spurious performance
of the NCO. Amplitude dither is enabled by writing Logic 1 in
the amplitude dither enable bit of the NCO control register of
the channel under consideration. Random amplitude is added
to the LSBs of the sine and cosine amplitudes, when this feature
is enabled. Amplitude dither improves performance by random-
izing the amplitude quantization errors within the angular-to-
Cartesian conversion of the NCO. This option might reduce
spurs at the expense of a slightly raised noise floor. Amplitude
dither and phase dither can be used together, separately, or not
at all.
NCO FREQUENCY HOLD-OFF REGISTER
When the NCO frequency registers are written by the micro-
port or serial port, data is passed to a shadow register. Data can
be moved to the main registers when the channel comes out of
sleep mode, or when a sync hop occurs. In either event, a
counter can be loaded with the NCO frequency hold-off
register value. The 16-bit unsigned integer counter starts
counting down, clocked by the input port clock selected at the
crossbar mux. When the counter reaches 0, the new frequency
value in the shadow register is written to the NCO frequency
register. Writing 1 in this hold-off register updates the NCO
frequency register as soon as the start sync or hop sync occurs.
See the Chip Synchronization section for details.
PHASE OFFSET
The phase offset register can be written with a value that is
added as an offset to the phase accumulator of the NCO. This
16-bit register is interpreted as a 16-bit unsigned integer. A
0x0000 in this register corresponds to a 0 radian offset and a
0xFFFF corresponds to an offset of 2π × (1 1/216) radians.
This register allows multiple NCOs (multiple channels) to be
synchronized to produce complex sinusoids with a known and
steady phase difference.
HOP SYNC
frequency of that channel needs to be changed from one
frequency to another. See the Chip Synchronization section for
details.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD6654BBCZ | 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD6654CBC | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD6654CBCZ | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
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