參數(shù)資料
型號: AD6644ASTZ-65
廠商: Analog Devices Inc
文件頁數(shù): 9/24頁
文件大小: 0K
描述: IC ADC 14BIT 65MSPS CMOS 52-LQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 1.3W
電壓電源: 模擬和數(shù)字
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應(yīng)商設(shè)備封裝: 52-LQFP(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,雙極
AD6644
Rev. D | Page 17 of 24
Jitter Considerations
The signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, Equation 1 accurately
predicts the SNR based on three terms. These are jitter, average
DNL error, and thermal noise. Each of these terms contributes
to the noise within the converter (see Equation 1).
() +
×
π
+
+
×
=
2
ε
1
log
20
rms
j
ANALOG
n
t
f
SNR
2
/
1
2
n
rms
NOISE
V
(1)
where:
fANALOG is the analog input frequency.
tj rms is the rms jitter of the encode (rms sum of encode source
and internal encode circuitry).
ε is the average DNL of the ADC (typically 0.41 LSB).
n is the number of bits in the ADC.
VNOISE rms is the V rms thermal noise referred to the analog input
of the ADC (typically 2.5 LSB).
For a 14-bit ADC like the AD6644, aperture jitter can greatly
affect the SNR performance as the analog frequency is
increased. Figure 31 shows a family of curves that demonstrates
the expected SNR performance of the AD6644 as jitter increases
and is derived from Equation 1.
For a complete review of aperture jitter, see Application Note
AN-756, Sampled Systems and the Effects of Clock Phase Noise
and Jitter, at www.analog.com.
JITTER (ps)
S
NR
(
d
B)
55
60
65
70
75
80
AIN = 190MHz
AIN = 150MHz
AIN = 110MHz
AIN = 30MHz
AIN = 70MHz
0
0.1
0.2
0.3
0.4
0.5
0.6
0097
1-
03
1
Figure 31. SNR vs. Jitter
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