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參數(shù)資料
| 型號： | AD6644ASTZ-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 65MSPS CMOS 52-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 1.3W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-LQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
AD6644
Rev. D | Page 16 of 24
input matches to a 50 Ω source with a full-scale drive of
4.8 dBm. Series resistors (RS) on the secondary side of the
transformer should be used to isolate the transformer from the
ADC. This limits the amount of dynamic current from the
ADC flowing back into the secondary of the transformer. The
terminating resistor (RT) should be placed on the primary side
of the transformer.
AIN
ADT4-1WT
AD6644
ANALOG INPUT
SIGNAL
RS
0.1F
RT
+
0097
1-
029
Figure 29. Transformer-Coupled Analog Input Circuit
In applications where dc coupling is required, the AD8138
differential output op amp from Analog Devices can be used
to drive the AD6644 (see Figure 30). The AD8138 op amp
provides single-ended-to-differential conversion, which reduces
overall system cost and minimizes layout requirements.
AD6644
AIN
AD8138
5V
499
VREF
DIGITAL
OUTPUTS
25
VOCM
CF
VIN
00
971-
03
0
0.1F
Figure 30. DC-Coupled Analog Input Circuit
Power Supplies
Care should be taken when selecting a power source. Linear
supplies are strongly recommended. Switching supplies tend to
have radiated components that may be received by the AD6644.
Each of the power supply pins should be decoupled as closely to
the package as possible using 0.1 μF chip capacitors.
The AD6644 has separate digital and analog power supply pins.
The analog supplies are denoted AVCC and the digital supply
pins are denoted DVCC. AVCC and DVCC should have separate
power supplies. This is because the fast digital output swings
can couple switching current back into the analog supplies.
Note that AVCC must be held within 5% of 5 V. The AD6644 is
specified for DVCC = 3.3 V because this is a common supply for
digital ASICs.
Digital Outputs
Care must be taken when designing the data receivers for the
AD6644. It is recommended that the digital outputs drive a
series resistor (for example, 100 Ω) followed by a gate like the
74LCX574. To minimize capacitive loading, there should only
be one gate on each output pin. An example of this is shown in
the evaluation board schematic of Figure 32. The digital outputs
of the AD6644 have a constant output slew rate of 1 V/ns.
A typical CMOS gate combined with a PCB trace have a load of
approximately 10 pF. Therefore, as each bit switches, 10 mA
(10 pF × 1 V ÷ 1 ns) of dynamic current per bit flow in or out
of the device. A full-scale transition can cause up to 140 mA
(14 bits × 10 mA/bit) of current to flow through the output
stages. The series resistors should be placed as close as possible
to the AD6644 to limit the amount of current that can flow into
the output stage. These switching currents are confined between
ground and the DVCC pin. Standard TTL gates should be avoided
because they can appreciably add to the dynamic switching
currents of the AD6644. Note that extra capacitive loading
increases output timing and invalidates timing specifications.
Digital output timing is guaranteed with 10 pF loads.
If the analog input range is exceeded, the overrange (OVR) bit
toggles high and the digital outputs retain their respective
positive or negative full-scale values.
Table 9. Twos Complement Output Coding
AIN Level
Output State
Output Code
VREF + 0.55 V
VREF 0.55 V
Positive FS
01 1111 1111 1111
VREF
Midscale
00…0/11…1
VREF 0.55 V
VREF + 0.55 V
Negative FS
10 0000 0000 0000
Layout Information
The schematic of the evaluation board (see Figure 32) represents a
typical implementation of the AD6644. A multilayer board is
recommended to achieve the best results. It is highly recom-
mended that high quality ceramic chip capacitors be used to
decouple each supply pin to ground directly at the device. The
pinout of the AD6644 facilitates ease of use in the implementation
of high frequency, high resolution design practices. All of the
digital outputs are segregated to two sides of the chip, with the
inputs on the opposite side for isolation purposes.
Care should be taken when routing the digital output traces.
To prevent coupling through the digital outputs into the analog
portion of the AD6644, minimal capacitive loading should be
placed on these outputs. It is recommended that a fanout of
only one gate be used for all AD6644 digital outputs. The layout
of the encode circuit is equally critical. Any noise received on
this circuitry results in corruption in the digitization process
and lower overall performance. The encode clock must be
isolated from the digital outputs and the analog inputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6644ASTZ-65 | 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD6644PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD6644ST | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD6644ST/PCB | 制造商:Analog Devices 功能描述:EVALUATION BOARD ((NW)) |
| AD6644ST/PCBZ | 制造商:Analog Devices 功能描述:14-BIT, 40 MSPS/65 MSPS A/D CONVERTER 制造商:Analog Devices 功能描述:AD6644 EVALUATION BOARD - Bulk |
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