參數(shù)資料
型號(hào)： AD6600ASTZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 7/24頁(yè)
文件大小： 0K
描述： IC ADC DUAL W/RSSI 44-LQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 11
采樣率（每秒）： 20M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 976mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-LQFP（10x10）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，雙極
REV. 0
AD6600
–15–
THEORY OF OPERATION
The AD6600, dual-channel, gain-ranging ADC integrates ana-
log IF circuitry with high speed data conversion. Each analog
input stage is a 1 GHz, 0 dB to –24 dB, phase-compensated step
attenuator; the step size in each attenuator is 12 dB. Both input
stages drive an analog multiplex function followed by a 12 dB/
18 dB gain amplifier. A simple LC noise filter at the output of
the gain amplifier is required to resonate at the desired IF. This
resonant filter port precedes a wide input bandwidth (450 MHz)
track-and-hold followed by an 11-bit analog-to-digital converter
(ADC). A high speed synchronous peak detector monitors sig-
nal strength at both input channels. The peak detector drives
RSSI circuitry that automatically adjusts attenuation and gain
on a clock-by-clock basis. The three RSSI indicator bits and the
eleven ADC bits are available at the output providing an exponent
and mantissa data format. Together these integrated components
form an IF sampling, high dynamic range ADC system.
It is helpful to view this device as a stand-alone ADC using
automatic gain control. The gain control referred to in this data
sheet as “gain-ranging” works to maintain a constant SNR over
as wide a range as possible.
As stated previously, the AD6600 has a floating-point output:
eleven mantissa bits and three exponent bits. As shown in Fig-
ure 16, at the lowest input levels SNR increases 1 dB for a 1 dB
increase in input power. In this range, the AD6600 is set for
maximum gain. However, when the input signal level reaches
the gain-ranging section (approximately –42 dBFS), the SNR is
contained between about 50 dB and 56 dB or between 44 dB and
56 dB including the effects of hysteresis. Although Figure 16
does not indicate so, there are slight differences between the
SNR from one gain range to the next as the gain amp switches
between 12 dB and 18 dB. Once the final RSSI range has been
exceeded (approximately –12 dBFS), SNR again increases 1 dB
per 1 dB input power increase until converter full scale is reached.
Again, this performance is very much like the effects of a typical
analog AGC loop.
GAIN
A/D
CONVERTER
TIMING
ENCODE
SELECT GAIN
+12, +18dB
ENCODE
FLT
NOISE FILTER
RESONANT
PORT
630
RSSI
3
TWO'S
COMPLEMENT
11
AB_OUT
D10–D0
RSSI [2:0]
CLK2
DVCC
ENC
GND
AVCC
B_SEL
A_SEL
ANALOG
MUX
GAIN
RSSI
3
0dB, –12dB, –24dB
ATTEN
0dB, –12dB, –24dB
DETECT
PEAK
SET
RSSI
AIN
BIN
AD6600
Figure 15. Functional Block Diagram
SNR – dB
–12
–48
24 28
AIN
–
dBFS
32 36 40 44 48 52 56 60
–18
–42
–54
–30
–36
–60
–24
–66
–72
–78
–84
–90
–96
0
–90
20
16
12
8
4
0
12dB SNR WINDOW
101
100
011
010
001
000
101
100
011
010
001
000
Figure 16. SNR for Gain-Ranging ADC
AD6600 SUBCIRCUITS
Input Step Attenuator and Gain Stage
The AD6600 has two identical input attenuators, Channel A
and Channel B. These dual inputs are typically used as diversity
channels but may also process two independent IF signals. For
maximum oversampling the device is used in single channel mode;
in this case only one input channel is required. The attenuator
steps are 0 dB, –12 dB and –24 dB. The attenuator settings are
based on the decisions of the RSSI stage (see Peak Detector/
RSSI section). The outputs of the attenuators connect to an
analog multiplexer that selects either Channel A or B for subse-
quent processing (see Input Mode). The selected signal drives
a dual-gain amplifier set to either 12 dB or 18 dB; the selected
gain is also determined by the RSSI stage. Therefore, based on
all possible combinations of attenuation and gain, the input
signal receives –12 dB to +18 dB of voltage gain in 6 dB steps
(Table I). Overall gain-matching is typically within 0.1 dB. With
a bandwidth of 1 GHz, the phase delay through the front-end
ranges from 0.2 degrees to 0.5 degrees, depending on input
frequency. Additionally, the input impedance does not change
with attenuator settings so there is no AM-to-PM distortion.
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AD6600ASTZ-REEL 功能描述:IC ADC DUAL W/RSSI 44-LQFP T/R RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極
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