I2C SERIAL INTERFACE TIMING CHARACTERISTICS
參數(shù)資料
型號： AD5934YRSZ
廠商： Analog Devices Inc
文件頁數(shù)： 29/32頁
文件大?。?/td> 0K
描述： IC NTWK ANALYZER 12B 1MSP 16SSOP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 12 b
主 fclk： 16.776MHz
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 管件
產(chǎn)品目錄頁面： 797 (CN2011-ZH PDF)
配用： EVAL-AD5934EBZ-ND - BOARD EVALUATION FOR AD5934
AD5934
Data Sheet
Rev. C | Page 6 of 32
I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted (see Figure 2).
Table 2.
Parameter1
Limit at T
MIN, TMAX
Unit
Description
f
SCL
400
kHz max
SCL clock frequency
t
1
2.5
s min
SCL cycle time
t
2
0.6
s min
t
HIGH, SCL high time
t
3
1.3
s min
t
LOW, SCL low time
t
4
0.6
s min
t
HD, STA, start/repeated start condition hold time
t
5
100
ns min
t
SU, DAT, data setup time
t
6
0.9
s max
t
HD, DAT, data hold time
0
s min
t
HD, DAT, data hold time
t
7
0.6
s min
t
SU, STA, setup time for repeated start
t
8
0.6
s min
t
SU, STO, stop condition setup time
t
9
1.3
s min
t
BUF, bus free time between a stop and a start condition
t
10
300
ns max
t
R, rise time of SDA when transmitting
0
ns min
t
R, rise time of SCL and SDA when receiving (CMOS compatible)
t
11
300
ns max
t
F, fall time of SCL and SDA when transmitting
0
ns min
t
F, fall time of SDA when receiving (CMOS compatible)
250
ns max
t
F, fall time of SDA when receiving
20 + 0.1 C
b
ns min
t
F, fall time of SCL and SDA when transmitting
C
b
400
pF max
Capacitive load for each bus line
1 Guaranteed by design and characterization, not production tested.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH MIN of the SCL signal) to bridge the undefined falling edge of SCL.
3 C
b is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.
05325-
002
SCL
SDA
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t9
t3
t10
t11
t4
t6
t2
t5
t7
t8
t1
Figure 2. I2C Interface Timing Diagram
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