The AD5934 uses two I2C read p" />
參數(shù)資料
型號: AD5934YRSZ
廠商: Analog Devices Inc
文件頁數(shù): 19/32頁
文件大?。?/td> 0K
描述: IC NTWK ANALYZER 12B 1MSP 16SSOP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 12 b
主 fclk: 16.776MHz
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
產(chǎn)品目錄頁面: 797 (CN2011-ZH PDF)
配用: EVAL-AD5934EBZ-ND - BOARD EVALUATION FOR AD5934
AD5934
Data Sheet
Rev. C | Page 26 of 32
READ OPERATIONS
The AD5934 uses two I2C read protocols: the receive byte and
the block read.
Receive Byte
In the AD5934, the receive byte protocol is used to read a single
byte of data from a register address whose address has previously
been set by setting the address pointer.
In this operation, the master device receives a single byte from a
slave device as follows (see Figure 29):
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master receives a data byte.
5. The master asserts a no acknowledge on SDA (the slave
needs to check that master has received data).
6. The master asserts a stop condition on SDA and the
transaction ends.
S
R
A
P
SLAVE
ADDRESS
REGISTER
DATA
05325-
052
Figure 29. Reading Register Data
Block Read
In this operation, the master device reads a block of data from a
slave device (see Figure 30). The start address for a block read
must previously have been set by setting the address pointer.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends a command code (1010 0001) that tells
the slave device to expect a block read.
5. The slave asserts an acknowledge on SDA.
6. The master sends a byte-count data byte that tells the slave
how many data bytes to expect.
7. The slave asserts an acknowledge on SDA.
8. The master asserts a repeat start condition on SDA. This is
required to set the read bit high.
9. The master sends the 7-bit slave address followed by the
read bit (high).
10. The slave asserts an acknowledge on SDA.
11. The master receives the data bytes.
12. The master asserts an acknowledge on SDA after each
data byte.
13. A no acknowledge is generated after the last byte to signal
the end of the read.
14. The master asserts a stop condition on SDA to end the
transaction.
NUMBER
BYTES READ
S
SLAVE
ADDRESS
W
A
BLOCK
READ
A
S
SLAVE
ADDRESS
R
A
BYTE 0
A
BYTE 1
A
BYTE 2
A
P
05325-
053
Figure 30. Performing a Block Read
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