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參數(shù)資料
| 型號： | AD5934YRSZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/32頁 |
| 文件大小： | 0K |
| 描述： | IC CONV 12BIT 250KSPS 16SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 500 |
| 分辨率（位）： | 12 b |
| 主 fclk： | 16.776MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-AD5934EBZ-ND - BOARD EVALUATION FOR AD5934 |
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Data Sheet
AD5934
Rev. C | Page 5 of 32
Y Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RECEIVE STAGE
Input Leakage Current
1
nA
To VIN pin
Input Capacitance5
0.01
pF
Pin capacitance between VOUT and GND
Feedback Capacitance, C
FB
3
pF
Feedback capacitance around current-to-
voltage amplifier; appears in parallel with
feedback resistor
ANALOG-TO-DIGITAL CONVERTER5
Resolution
12
Bits
Sampling Rate
250
kSPS
ADC throughput rate
LOGIC INPUTS
Input High Voltage, V
IH
0.7 × VDD
Input Low Voltage, V
IL
0.3 × VDD
Input Current6
1
A
T
A = 25°
Input Capacitance
7
pF
T
A = 25°C
POWER REQUIREMENTS
VDD
2.7
5.5
V
I
DD, Normal Mode
10
15
mA
VDD = 3.3 V
17
25
mA
VDD = 5.5 V
I
DD, Standby Mode
7
mA
VDD = 3.3 V; see the Control Register section
9
mA
VDD = 5.5 V
I
DD, Power-Down Mode
0.7
5
A
VDD = 3.3 V
1
8
A
VDD = 5.5 V
1 Temperature range for Y version = 40°C to +125°C, typical at +25°C.
2 The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5934.
3 The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage.
Output Excitation Voltage (V p-p) = [2/3.3] × VDD
4 The dc bias value of the output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage.
Output Excitation Voltage (V p-p) = [2/3.3] × VDD
5 Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of current-
to-voltage amplifier.
6 The accumulation of the currents into Pin 8, Pin 15, and Pin 16.
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