參數(shù)資料
型號(hào)： AD5934YRSZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 0K
描述： IC CONV 12BIT 250KSPS 16SSOP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 500
分辨率（位）： 12 b
主 fclk： 16.776MHz
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
配用： EVAL-AD5934EBZ-ND - BOARD EVALUATION FOR AD5934
AD5934
Data Sheet
Rev. C | Page 22 of 32
NUMBER OF INCREMENTS REGISTER (REGISTER
ADDRESS 0x88, REGISTER ADDRESS 0x89)
The default value of the number of increments register upon
reset is as follows: D8 to D0 are not reset at power-up. After a
reset command, the contents of this register are not reset.
Table 11. Number of Increments Register
Reg Addr
Bits
Description
Function
Format
0x88
D15 to D9
Don’t care
Read or
write
Integer
number
stored
in binary
format
D8
Number of
increments
Read or
write
0x89
D7 to D0
Number of
increments
Read or
write
Integer
number
stored
in binary
format
This register determines the number of frequency points in the
frequency sweep. The number of frequency points is represented
by a 9-bit word, D8 to D0. D15 to D9 are don’t care bits. This
register in conjunction with the start frequency register and the
frequency increment register determine the frequency sweep
range for the sweep operation. The maximum number of
increments that can be programmed is 511.
NUMBER OF SETTLING TIME CYCLES REGISTER
(REGISTER ADDRESS 0x8A, REGISTER ADDRESS
0x8B)
The default value of the number of settling time cycles register
upon reset is as follows: D10 to D0 are not reset at power-up.
After a reset command, the contents of this register are not reset.
This register determines the number of output excitation cycles
allowed to passthrough the unknown impedance after receipt of
a start frequency sweep, increment frequency, or repeat frequency
command, before the ADC is triggered to perform a conversion
of the response signal. The number of settling time cycles register
value determines the delay between a start frequency sweep/
increment frequency/repeat frequency command and the time
an ADC conversion commences. The number of cycles is
represented by a 9-bit word, D8 to D0. The value programmed
into the number of settling time cycles register can be increased
by a factor of 2 or 4, depending on the status of Bits D10 to D9.
The five most significant bits, D15 to D11, are don’t care bits.
The maximum number of output cycles that can be programmed is
511 × 4 = 2044 cycles. For example, consider an excitation signal of
30 kHz, the maximum delay between the programming of this
frequency and the time that this signal is first sampled by the
ADC is ≈ 511 × 4 × 33.33 s = 68.126 ms. The ADC takes 1024
samples, and the result is stored as real data and imaginary data in
Register Address 0x94 to Register Address 0x97. The conversion
process takes approximately 1 ms using a 16.777 MHz clock.
STATUS REGISTER (REGISTER ADDRESS 0x8F)
The status register is used to confirm that particular measurement
tests have been successfully completed. Each of the bits from D7 to
D0 indicate the status of a specific functionality of the AD5934.
Bit D0 and Bit D4 to Bit D7 are treated as don’t care bits; these
bits do not indicate the status of any measurement.
The status of Bit D1 indicates the status of a frequency point
impedance measurement. This bit is set when the AD5934
completes the current frequency point impedance measurement.
This bit indicates that there is valid real data and imaginary data
in Register Address 0x94 to Register Address 0x97. This bit is
reset on receipt of a start frequency sweep, increment frequency,
repeat frequency, or reset command. This bit is also reset at
power-up.
The status of Bit D2 indicates the status of the programmed
frequency sweep. This bit is set when all programmed increments
to the number of increments register are complete. This bit is
reset at power-up and on receipt of a reset command.
Table 12. Status Register 0x8F
Control Word
Description
0000 0001
Reserved
0000 0010
Valid real/imaginary data
0000 0100
Frequency sweep complete
0000 1000
Reserved
0001 0000
Reserved
0010 0000
Reserved
0100 0000
Reserved
1000 0000
Reserved
Table 13. Number of Settling Times Cycles Register
Register Address
Bits
Description
Function
Format
0x8A
D15 to D11
Don’t care
Read or write
Integer number stored in binary format
D10 to D9
2-bit decode
D10
D9
Description
0
Default
0
1
No of cycles ×2
1
0
Reserved
1
No of cycles ×4
D8
MSB number of settling time cycles
0x8B
D7 to D0
Number of settling time cycles
Read or write
Data
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