I2C SERIAL INTERFACE TIMING CHARACTERISTICS
參數(shù)資料
型號(hào)： AD5933YRSZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 37/40頁(yè)
文件大?。?/td> 0K
描述： NETWORK ANALYZER 12B 1MSP 16SSOP
產(chǎn)品培訓(xùn)模塊： AD5933 Impedance to Digital Converter
Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 500
分辨率（位）： 12 b
主 fclk： 16.776MHz
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
配用： EVAL-AD5933EBZ-ND - BOARD EVALUATION FOR AD5933
AD5933
Data Sheet
Rev. E | Page 6 of 40
I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter2
Limit at TMIN, TMAX
Unit
Description
fSCL
400
kHz max
SCL clock frequency
t1
2.5
μs min
SCL cycle time
t2
0.6
μs min
tHIGH, SCL high time
t3
1.3
μs min
tLOW, SCL low time
t4
0.6
μs min
tHD, STA, start/repeated start condition hold time
t5
100
ns min
tSU, DAT, data setup time
0.9
μs max
tHD, DAT, data hold time
0
μs min
tHD, DAT, data hold time
t7
0.6
μs min
tSU, STA, setup time for repeated start
t8
0.6
μs min
tSU, STO, stop condition setup time
t9
1.3
μs min
tBUF, bus free time between a stop and a start condition
t10
300
ns max
tF, rise time of SDA when transmitting
0
ns min
tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11
300
ns max
tF, fall time of SCL and SDA when transmitting
0
ns min
tF, fall time of SDA when receiving (CMOS compatible)
250
ns max
tF, fall time of SDA when receiving
20 + 0.1 Cb4
ns min
tF, fall time of SCL and SDA when transmitting
Cb
400
pF max
Capacitive load for each bus line
2 Guaranteed by design and characterization, not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL.
4 Cb is the total capacitance of one bus line in picofarads. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.
SCL
SDA
t9
t3
t10
t11
t4
t6
t2
t5
t7
t8
t1
05
32
4-
0
02
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 2. I2C Interface Timing Diagram
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