- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1979 > AD570JD (Analog Devices Inc)IC ADC 8BIT MONO W/CLK 18-CDIP PDF資料下載
參數(shù)資料
| 型號： | AD570JD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT MONO W/CLK 18-CDIP |
| 產(chǎn)品變化通告： | Redesign Change 26/Apr/2012 |
| 標準包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 40k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 18-CDIP（0.300"，7.62mm） |
| 供應商設(shè)備封裝： | 18-CDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
AD570
REV.
–6–
the DR and data lines will not change. If a 2
s or longer pulse
is applied to the B & C line during a conversion, the converter
will clear and start a new conversion cycle.
Figure 9. AD570 Timing and Control Sequence
CONTROL MODES WITH BLANK AND CONVERT
The timing sequence of the AD570 discussed above allows the
device to be easily operated in a variety of systems with differing
control modes. The two most common control modes, the Con-
vert Pulse Mode, and the Multiplex Mode, are illustrated here.
Convert Pulse Mode–In this mode, data is present at the output
of the converter at all times except when conversion is taking
place. Figure 10 illustrates the timing of this mode. The BLANK
and CONVERT line is normally low and conversions are trig-
gered by a positive pulse. A typical application for this timing
mode is shown in Figure 13, in which
P bus interfacing is
easily accomplished with three-state buffers.
Multiplex Mode—In this mode the outputs are blanked except
when the device is selected for conversion and readout; this tim-
ing is shown in Figure 11. A typical AD570 multiplexing appli-
cation is shown in Figure 14.
This operating mode allows multiple AD570 devices to drive
common data lines. All BLANK and CONVERT lines are held
high to keep the outputs blanked. A single AD570 is selected, its
BLANK and CONVERT line is driven low and at the end of
conversion, which is indicated by DATA READY going low, the
conversion result will be present at the outputs. When this data
has been read from the 8-bit bus, BLANK and CONVERT is
restored to the blank mode to clear the data bus for other con-
verters. When several AD570s are multiplexed in sequence, a
new conversion may be started in one AD570 while data is
being read from another. As long as the data is read and the first
AD570 is cleared within 15
s after the start of conversion of the
second AD570, no data overlap will occur.
Figure 10. Convert Pulse Mode
Figure 11. Multiplex Mode
SAMPLE-HOLD AMPLIFIER CONNECTION TO THE
AD570
Many situations in high-speed acquisition systems or digitizing
of rapidly changing signals require a sample-hold amplifier
(SHA) in front of the A-D converter. The SHA can acquire and
hold a signal faster than the converter can perform a conversion.
A SHA can also be used to accurately define the exact point in
time at which the signal is sampled. For the AD570, a SHA can
also serve as a high input impedance buffer.
Figure 12 shows the AD570 connected to the AD582 mono-
lithic SHA for high speed signal acquisition. In this configura-
tion, the AD582 will acquire a 10 volt signal in less than 10
s
with a droop rate less than 100
V/ms. The control signals are
arranged so that when the control line goes low, the AD582 is put
into the “hold” mode, and the AD570 will begin its conversion
cycle. (The AD582 settles to final value well in advance of the
Figure 12. Sample-Hold Interface to the AD570
first comparator decision inside the AD570). The DATA
READY
line is fed back to the other side of the differential
input control gate so that the AD582 cannot come out of the
“hold” mode during the conversion cycle. At the end of the con-
version cycle, the DATA READY line goes low, automatically
placing the AD582 back into the sample mode. This feature al-
lows simple control of both the SHA and the A-D converter
with a single line. Observe carefully the ground, supply, and by-
pass capacitor connections between the two devices. The ar-
rangement minimizes ground noise and interference during the
conversion cycle to give the most accurate measurements.
B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD571JD | IC ADC 10BIT MONO W/CLK 18-CDIP |
| AD5725BRSZ-REEL | IC DAC 12BIT QUAD PAR 28-SSOP |
| AD5735ACPZ-REEL7 | IC DAC QUAD VOLT CUR 64LFCSP |
| AD5737ACPZ | IC DAC QUAD 12BIT CUR 64-LFCSP |
| AD573JD | IC ADC 10BIT SAR REG 20-CDIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD570JD/+ | 制造商:Analog Devices 功能描述:ADC SGL SAR 8BIT PARALLEL 18PIN SBCDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:IC, MONO 8-BIT A/D CONV - Bulk |
| AD570JD883B | 制造商:AD 功能描述:_ |
| AD570JD-883B | 制造商:AD 功能描述:_ |
| AD570S | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 8-Bit A-to-D Converter |
| AD570SCHIPS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
發(fā)布緊急采購，3分鐘左右您將得到回復。