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參數(shù)資料
| 型號： | AD5700BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HART MODEM LP 24LFCSP |
| 標準包裝： | 1,500 |
| 系列： | * |
AD5700/AD5700-1
Data Sheet
Rev. F | Page 18 of 24
As previously mentioned, Figure 29 shows an example secondary
HART device, incorporating two-stage protection circuitry. In
this example, a bidirectional (for protection against both positive
and negative high voltage transients) TVS is included to provide
flexibility in the polarity of the connection points of the module.
Because this module could be connected to any point on the
current loop, the higher TVS rating was chosen. The lower
rated second stage provides added protection for the AD5700/
AD5700-1 device.
TYPICAL CONNECTION DIAGRAMS
Figure 30 shows a typical connection diagram for the AD5700/
AD5700-1 using the external and internal options. See the
Connecting to HART_IN or ADC_IP section for more details.
The AD5700/AD5700-1 are designed to interface easily with
Analog Devices, Inc., innovative portfolio of industrial
converters like the AD5421 loop-powered current-output DAC,
powered current-output DACs, and the AD5755-1, a quad DAC
with innovative dynamic power control technology. The
combination of Analog Devices industrial converters and the
AD5700/AD5700-1 greatly simplifies system design, enhancing
reliability while reducing overall PCB size.
can be interfaced with the AD5421 (4 mA to 20 mA loop-powered
DAC) and the ADuCM360 microcontroller to construct a loop
powered transmitter circuit. The HART signal from
The HART enabled smart transmitter reference demo circuit
(the block diagram shown in Figure 32) was developed by
Analog Devices and uses the AD5421, a 16-bit, loop-powered,
4 mA to 20 mA DAC, the ADuCM360 microcontroller and the
AD5700 modem. This circuit has been compliance tested,
verified, and registered as an approved HART solution by the
HART Communication Foundation. Contact your sales
representative for further information about this demo circuit.
In conclusion, the AD5700/AD5700-1 enable quick and easy
deployment of a robust HART-compliant system.
Figure 30. AD5700/AD5700-1 Typical Connection Diagram for External and Internal Filter Options
10435-
023
10F
0.1F
1F
10F
150pF
1F
1.71V TO 5.5V
RE
G
_CAP
R
ESET
IOVCC
VCC
AGND
AD5700/AD5700-1
CL
KO
UT
X
TA
L1
X
TA
L2
+
150k
1.2M
300pF
REF
HART_OUT
DGND
CONFIGURATION
PINS
RE
F
_E
N
FILTE
R
_
S
E
L
DUP
L
E
X
CL
K_CF
G
0
CL
K_CF
G
1
X
T
AL
_E
N
HART_IN
ADC_IP
CD
RXD
TXD
RTS
ADu
C7060
M
ICRO
CO
NT
RO
L
E
R
10F
0.1F
1F
HART
NE
T
W
O
RK
HART
NE
T
W
O
RK
1.71V TO 5.5V
RE
G
_CAP
R
ESET
IOVCC
VCC
AGND
AD5700/AD5700-1
CL
KO
UT
X
TA
L1
X
TA
L2
+
REF
HART_OUT
DGND
CONFIGURATION
PINS
RE
F
_E
N
FILTE
R
_
S
E
L
DUP
L
E
X
CL
K_CF
G
0
CL
K_CF
G
1
X
T
AL
_E
N
HART_IN
ADC_IP
CD
RXD
TXD
RTS
ADu
C7060
M
ICRO
CO
NT
RO
L
E
R
680pF
2.2nF
1F
+
0.1F
10F
1.71V TO 5.5V
+
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