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參數(shù)資料
| 型號： | AD5641 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.7 V to 5.5 V, <100 uA, 14-Bit nanoDAC D/A in SC70 Package |
| 中文描述： | 2.7 V至5.5 V，“100微安，14位nanoDAC系列數(shù)/采用SC70阿包 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 572K |
| 代理商： | AD5641 |
AD5641
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrC | Page 6 of 20
TOP VIEW
(Not to Scale)
V
DD
GND
SCLK
DIN
AD5641
V
OUT
SYNC
1
2
3
6
5
4
0
Figure 3. 6-Lead SC70 Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1
SYNC
Function
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow.
The DAC is updated following the 16
th
clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. V
DD
should be decoupled to GND.
Ground Reference Point for All Circuitry on the AD5641.
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
2
SCLK
3
DIN
4
5
6
V
DD
GND
V
OUT
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