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參數(shù)資料
| 型號： | AD5641 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.7 V to 5.5 V, <100 uA, 14-Bit nanoDAC D/A in SC70 Package |
| 中文描述： | 2.7 V至5.5 V，“100微安，14位nanoDAC系列數(shù)/采用SC70阿包 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 572K |
| 代理商： | AD5641 |
AD5641
Preliminary Technical Data
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted. See Figure 2.
Table 3.
Parameter
Limit
1
Unit
t
12
33
ns min
t
2
13
ns min
t
3
12
ns min
t
4
13
ns min
t
5
5
ns min
t
6
4.5
ns min
t
7
0
ns min
t
8
33
ns min
t
9
13
ns min
Rev. PrC | Page 4 of 20
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 30 MHz.
t
4
t
3
t
2
t
5
t
7
t
6
D0
D1
D2
D14
D15
DIN
SYNC
SCLK
0
t
9
t
1
t
8
D15
D14
Figure 2. Timing Diagram
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