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參數(shù)資料
| 型號： | AD5501BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SPI 16-TSSOP |
| 產(chǎn)品培訓模塊： | DAC Architectures |
| 標準包裝： | 96 |
| 設置時間： | 45µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | * |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | * |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
Data Sheet
AD5501
Rev. C | Page 13 of 20
THEORY OF OPERATION
The AD5501 contains a 12-bit DAC, an output amplifier, and a
precision reference in a single package. The architecture of the
DAC channel consists of a 12-bit resistor string DAC followed
by an output buffer amplifier. The part operates from a single-
supply voltage of 10 V to 62 V. The DAC output voltage range is
selected via the range select, R_SEL, pin. The DAC output range
is 0 V to 30 V if R_SEL is held high and 0 V to 60 V if R_SEL is
held low. Data is written to the AD5501 in a 16-bit word format
(see Table 8), via a serial interface.
POWER-UP STATE
On power-up, the power-on reset circuitry clears the bits of the
control register to 0x40 (see Table 10) ensuring that the analog
section is initially powered down, which helps reduce power
consumption. The user can program the DAC register to the
required value while typically consuming only 30 A of supply
current. The power-on reset circuitry also ensures that the input
and DAC registers power up in a known condition, 0x000, and
remain there until a valid write to the device has taken place.
The analog section can be powered up by setting Bit C2 of the
control register to 1.
POWER-DOWN MODE
The DAC channel can be powered up or powered down by
programming Bit C2 in the control register (see Table 10). When
the DAC channel is powered down, the associated analog circuitry
turns off to reduce power consumption. The digital section of
the AD5501 remains powered up. The output of the DAC amplifier
can be three-stated or connected to AGND via an internal 20 k
resistor, depending on the state of Bit C6 in the control register.
The power-down mode does not change the contents of the DAC
register to ensure that the DAC channel returns to its previous
voltage when the power-down bit is set to 1. The AD5501 also
offers the user the flexibility of updating the DAC registers during
power-down. The control register can be read back at any time
to check the status of the bits.
DAC CHANNEL ARCHITECTURE
The architecture of the DAC channel consists of a 12-bit resistor
string DAC followed by an output buffer amplifier (see Figure 14).
The resistor string section is simply a string of resistors, each of
Value R from VREF generated by the precision reference to AGND.
This type of architecture guarantees DAC monotonicity. The 12-bit
binary digital code loaded to the DAC register determines at which
node on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the DAC
output voltage to give a fixed linear voltage output range of 0 V
to 60 V if R_SEL = 0 or 0 V to 30 V if R_SEL = 1. Each output
amplifier is capable of driving a 60 kΩ load while allowing an
output swing within the range of AGND + 0.5 V to VDD 0.5 V.
Because the DAC architecture gives a fixed voltage output range
of 0 V to 30 V or 0 V to 60 V, the user should set VDD to at least
30.5 V or 60.5 V to use the maximum DAC resolution. The data
format for the AD5501 is straight binary and the output voltage
follows the formula
Range
D
VOUT
×
=
4096
where:
D is the code loaded to the DAC.
Range = 30, if R_SEL is high, and 60 if R_SEL is low.
GAIN
VOUT
DAC
REGISTER
INPUT
REGISTER
PRECISION
REFERENCE
AGND
12
DAC
07992-
014
Figure 14. DAC Channel Architecture
VFB PIN
The voltage feedback pin (VFB) is part of the feedback loop of
the gain amplifier. To compensate for any voltage drop between the
VOUT pin and the load, connect (in a force sense configuration) VFB
VFB
RL
OUTPUT
BUFFER
12-BIT
DAC
1713k
122.36k
VOUT
07992-
015
Figure 15. VFB and VOUT Configuration
The VFB pin can also be used to control a pass transistor where
more current is required than can be supplied by the AD5501.
The configuration is shown in Figure 16.
VFB
OUTPUT
BUFFER
12-BIT
DAC
1713k
122.36k
VOUT
RL
VDD
07992-
016
R
Figure 16. Pass Transistor Configuration
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD5501BRUZ | 制造商:Analog Devices 功能描述:IC DAC 12BIT TSSOP-16 |
| AD5501BRUZ-REEL | 功能描述:12 Bit Digital to Analog Converter 1 16-TSSOP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時間 位數(shù):12 數(shù)模轉換器數(shù):1 建立時間:55μs 輸出類型:Voltage - Buffered 差分輸出:無 數(shù)據(jù)接口:SPI，DSP 參考類型:內(nèi)部 電壓 - 電源，模擬:10 V ~ 62 V 電壓 - 電源，數(shù)字:2.3 V ~ 5.5 V INL/DNL（LSB）:±2（最大），±1（最大） 架構:電阻串 DAC 工作溫度:-40°C ~ 105°C 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商器件封裝:16-TSSOP 標準包裝:1 |
| AD5504BRUZ | 功能描述:IC DAC 12BIT SPI 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5504BRUZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Voltage, Quad-Channel 12-Bit Voltage Output DAC |
| AD5512A | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDACs in LFCSP |
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