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參數(shù)資料
| 型號(hào)： | AD5380EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC |
| 中文描述： | 40通道，3V/5V單電源，14位，電壓輸出DAC |
| 文件頁數(shù)： | 9/34頁 |
| 文件大?。?/td> | 975K |
| 代理商： | AD5380EB |
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PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
AD5380
–9–
PARALLEL INTERFACE
Parameter
1,2,3
Limit at T
MIN,
T
MAX
Units
Description
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
94
t
104
t
114,5
t
124
t
13
t
144
t
15
t
16
t
174
t
18
t
19
t
20
4.5
4.5
20
20
0
0
4.5
4.5
20
430
30
400
30
20
100
20
0
100
8
20
12
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns min
μs typ
ns min
μs
max
REG0,REG1,Address to
WR
Rising Edge Setup Time
REG0,REG1, Address to
WR
Rising Edge Hold Time
CS
Pulse Width Low
WR
Pulse Width Low
CS
to
WR
Falling Edge Setup Time
WR
to
CS
Rising Edge Hold Time
Data to
WR
Rising Edge Setup Time
Data to
WR
Rising Edge Hold Time
WR
Pulse Width High
Minimum
WR
Cycle Time (Single Channel Write)
WR
Rising Edge to
BUSY
Falling Edge
BUSY
Pulse Width Low (Single Channel Update)
WR
Rising
Edge to
LDAC
Falling Edge
LDAC
Pulse Width Low
BUSY
Rising Edge
to DAC Output Response Time
LDAC
Rising Edge
to
WR
Rising Edge
BUSY
Rising Edge to
LDAC
Falling Edge
LDAC
Falling Edge to
DAC Output Response Time
DAC Output Settling Time, Boost Mode Off.
CLR
Pulse Width Low
CLR
Pulse Activation Time
(DV
DD
= 2.7 V to +5.5V; AV
DD
=+4.5V to +5.5V or +2.7V to +3.6V; AGND = DGND = 0 V;
All specifications T
MIN
to T
MAX
unless otherwise noted.)
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.2 V.
3
See Timing Diagram in Figure 6.
4
See Table XXX.
5
This is measured with the load circuit of Figure 1a.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Figure 6. Parallel Interface Timing Diagram
t4
t7
t6
DB13..DB0
t5
REG0, REG1, A5..A0
CS
LDAC1
t2
CLR
t20
t19
t3
WR
t10
LDAC2
1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE AFTER BUSY
VOUT1
t17
VOUT2
t8
BUSY
t11
t12
t13
t13
t16
t14
t18
t18
VOUT
t9
t1
t0
t15
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