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參數(shù)資料
| 型號： | AD5380EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC |
| 中文描述： | 40通道，3V/5V單電源，14位，電壓輸出DAC |
| 文件頁數(shù)： | 24/34頁 |
| 文件大?。?/td> | 975K |
| 代理商： | AD5380EB |
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PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
–24–
AD5380
Figure 10 . AD5380, Serial Readback Operation
Selected Register Data
Clocked out.
DB23
DB0
DB23'
DB0'
48
NOP Condition
UNDEFINED
SDO
SCLK
SYNC
DIN
DB23
DB0
Input Word Specifies
Register to be Read
24
clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out
on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input
on the next device in the chain, a multi-device interface is constructed. 24 clock pulses are required for each device in the
system. Therefore, the total number of clock cycles must equal 24N where N is the total number of AD538X devices in
the chain.
When the serial transfer to all devices is complete,
SYNC
is taken high. This latches the input data in each device in the
daisy-chain and prevents any further data being clocked into the input shift register.
If the SYNC is taken high before 24 clocks are clocked into the part this is considered as a bad frame and the data is
discarded.
The serial clock may be either a continuous or a gated clock. A continuous SCLK source can only be used if it can be
arranged that
SYNC
is held low for the correct number of clock cycles. In gated clock mode a burst clock containing the
exact number of clock cycles must be used and
SYNC
taken high after the final clock to latch the data.
Readback Mode
Readback mode is invoked by setting the R/
W
bit = 1 in the serial input register write. With R/
W
=1, the bits A5-A0 in
association with bits REG1 and REG0 selects the register to be read. The remaining data bits in the write sequence are
dont cares. During the next SPI write the data appearing on the SDO output will contain the data from the previously
addressed register. For a read of a single register the NOP command can be used in clocking out the data from the
selected register on SDO. The readback diagram in figure 10 shows the readback sequence. For example, to readback
the M register of channel 0 on the AD5380 the following sequence should be implemented. Firstly write 404XXX Hex
to the AD5380 input register. This configures the AD5380 for read mode with M register of channel zero selected. Note
all the data bits DB13 to DB0 are dont cares. Follow this with a second write, a NOP condition, 000000 Hex, during
this write the data from the M register is clocked out on the DOUT line, ie data clocked out will contain the data from
the M register in bits DB13 to DB0, and the top 10 bits contain the address information as previously written. In
readback mode the SYNC signal must frame the data. Data is clocked out on the rising edge of SCLK and is valid on
the falling edge of the SCLK signal. Is the SCLK idles high between the write and read operations of a readback
operation then the first bit of data is clocked out on the falling edge of SYNC.
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| AD5381BSTZ-3 | 功能描述:IC DAC 12BIT 40CHAN 3V 100LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 數(shù)模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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