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參數(shù)資料
| 型號(hào)： | AD5380EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC |
| 中文描述： | 40通道，3V/5V單電源，14位，電壓輸出DAC |
| 文件頁(yè)數(shù)： | 8/34頁(yè) |
| 文件大?。?/td> | 975K |
| 代理商： | AD5380EB |
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PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
–8–
AD5380
F
SCL
t
1
t
2
t
3
t
4
t
5
t
63
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
SCL Clock Frequency
SCL Cycle Time
t
HIGH
, SCL High Time
t
LOW
, SCL Low Time
t
HD,STA
, Start/Repeated Start Condition Hold Time
t
SU,DAT
, Data Setup Time
t
HD,DAT
, Data Hold Time
t
HD,DAT
, Data Hold Time
t
SU,STA
, Setup Time for Repeated Start
t
SU,STO
, Stop Condition Setup Time
t
BUF
, Bus Free Time Between a STOP and a START Condition
t
R
, Rise Time of SCL and SDA when Receiving
t
R
, Rise Time of SCL and SDA when Receiving (CMOS-Com
patible)
t
F
, Fall Time of SDA when Transmitting
t
F
, Fall Time of SDA when Receiving (CMOS-Compatible)
t
F
, Fall Time of SCL and SDA when Receiving
t
F
, Fall Time of SCL and SDA when Transmitting
Capacitive Load for Each Bus Line
t
7
t
8
t
9
t
10
t
11
300
0
300
20 + 0.1C
b4
400
ns max
ns min
ns max
ns min
pF max
C
B
TIMING CHARACTERISTICS
(DV
DD
= 2.7V to 5.5V ; AV
DD
=+4.5V to +5.5V or +2.7V to +3.6V; AGND= DGND = 0 V; )
All specifications T
MIN
to T
MAX
unless otherwise noted.)
I2C SERIAL INTERFACE
Parameter
1,2
Limit at T
MIN,
T
MAX
Units
Description
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Figure 5
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
MIN of the SCL signal) in order to bridge the
undefined region of SCL’s falling edge.
4
Cb is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 VDD and 0.7 VDD.
SCL
SDA
START
CONDITION
t
9
t
3
t
4
t
6
t
2
t
5
t
7
t
8
t
1
t
4
t
11
t
10
REPEATED
START
CONDITION
STOP
CONDITION
Figure 5. I2C Compatible Serial Interface Timing Diagram
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