參數(shù)資料
型號(hào): AD5380BST-5
廠商: ANALOG DEVICES INC
元件分類(lèi): DAC
英文描述: 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC
中文描述: PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100
封裝: 14 X 14 MM, MS-026BED, LQFP-100
文件頁(yè)數(shù): 28/34頁(yè)
文件大小: 975K
代理商: AD5380BST-5
PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
–28–
AD5380
AD538X
CONTROLLER/
DSP PROCESSOR*
ADDRESS
DECODE
D15
D0
DATA
BUS
UPPER BITS OF
ADDRESS BUS
A2
A1
A0
R/W
*ADDITIONAL PINS OMITTED FOR CLARITY
D13
D0
CS
LDAC
A2
A1
A0
WR
A3
A4
A5
REG1
REG0
A3
A4
A5
AD5380 PARALLEL INTERFACE
The SER/
PAR
pin must be tied low to enable the parallel interface and disable the serial interfaces. Figure 5 shows the
timing diagram for a parallel write. The parallel interface is controlled by the following pins:
Pin
Active low device select pin.
Pin
On the rising edge of
WR
, with
CS
low, the address on pins A5-A0 are latched and data present on the data bus is
loaded into the selected input registers.
REG0, REG1 Pins
The REG0 and REG1 pins determine the destination register of the data being written to the AD5380. See Table I.
A5-A0 Pins
Each of the 40 DAC channels can be addressed individually.
DB13-DB0 Pins
The AD5380 accepts a straight 14-bit parallel word on DB13-DB0 where DB13 is the MSB and DB0 is the LSB.
CS
WR
MICROPROCESSOR INTERFACING
Parallel Interface
Figure 14 . AD5380 -Parallel Interface
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