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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD5200BRMZ10
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 5/15闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC POT DGTL 10K 256POS 10MSOP
妯欐簴鍖呰锛� 50
鎺ョ墖锛� 256
闆婚樆锛堟瓙濮嗭級锛� 10k
闆昏矾鏁�(sh霉)锛� 1
婧害绯绘暩(sh霉)锛� 妯欐簴鍊� 500 ppm/°C
瀛樺劜鍣ㄩ鍨嬶細 鏄撳け
鎺ュ彛锛� 3 绶氫覆琛岋紙鑺墖閬告搰锛�
闆绘簮闆诲锛� 2.7 V ~ 5.5 V锛�±2.3 V ~ 2.7 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 10-MSOP
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 786 (CN2011-ZH PDF)
AD5200/AD5201
鈥�13鈥�
AD5200 Wiper-to-A Resistance
DRWA
(DEC)
( )
Output State
255
50
Full-Scale (RW)
128
5030
Midscale
1
10011
1 LSB
0
10050
Zero-Scale (RAB + RW)
AD5201 Wiper-to-A Resistance
DRWA
(DEC)
( )
Output State
32
50
Full-Scale (RW)
16
5050
Midscale
1
9738
1 LSB
0
10050
Zero-Scale (RAB + RW)
The tolerance of the nominal resistance can be
卤30% due to
process lot dependance. If users apply the RDAC in rheostat
(variable resistance) mode, they should be aware of such specifi-
cation of tolerance. The change in RAB with temperature has a
500 ppm/
掳C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates output voltages at
wiper-to-B and wiper-to-A to be proportional to the input volt-
age at A to B.
Unlike the polarity of VDD 鈥� VSS, which must be positive, volt-
age across A鈥揃, W鈥揂, and W鈥揃 can be at either polarity.
If ignoring the effects of the wiper resistance for an approxima-
tion, connecting A terminal to 5 V and B terminal to ground
produces an output voltage at the wiper which can be any value
starting at almost zero to almost full scale with the minor devia-
tion contributed by the wiper resistance. Each LSB of voltage is
equal to the voltage applied across Terminal AB divided by the
2
N-1 and 2N position resolution of the potentiometer divider for
AD5200 and AD5201 respectively. The general equation defin-
ing the output voltage with respect to ground for any valid input
voltage applied to Terminals A and B is:
VD
D
VV
WAB
B
() =+
255
for AD5200
(5)
VD
D
VV
WAB
B
() =+
32
for AD5201
(6)
where D in AD5200 is between 0 to 255 and D in AD5201 is
between 0 to 32.
For more accurate calculation, including the effects of wiper
resistance, VW can be found as:
VD
RD
R
V
RD
R
V
W
WB
AB
A
WA
AB
B
() = () + ()
(7)
where RWB(D) and RWA(D) can be obtained from Equations
1 to 4.
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Here the output
voltage is dependent on the ratio of the internal resistors and not
the absolute values; therefore, the drift reduces to 15 ppm/
掳C.
DIGITAL INTERFACING
The AD5200/AD5201 contain a standard three-wire serial input
control interface. The three inputs are clock (CLK),
CS, and
serial data input (SDI). The positive-edge-sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means.
Figure 3 shows more detail of the internal digital circuitry. When
CS is low, the clock loads data into the serial register on each
positive clock edge (see Table III).
SER
REG
PWR-ON
PRESET
VSS
A
W
B
SHDN
RDAC
REG
Dx
8/6
VDD
CS
CLK
SDI
GND
AD5200/AD5201
Figure 3. Block Diagram
Table III. Input Logic Control Truth Table
CLK
CS
SHDN
Register Activity
L
H
No SR effect.
P
L
H
Shift one bit in from the SDI pin.
X
P
H
Load SR data into RDAC latch.
X
H
No operation.
X
H
L
Open circuit on A terminal and short
circuit between W to B terminals.
NOTE
P = positive edge, X = don鈥檛 care, SR = shift register.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 4. Applies to
digital input pins
CS, SDI, SHDN, CLK.
340
LOGIC
VSS
Figure 4. ESD Protection of Digital Pins
A,B,W
VSS
Figure 5. ESD Protection of Resistor Terminals
鐩搁棞PDF璩囨枡
PDF鎻忚堪
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鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
AD5200BRMZ10-REEL7 鍔熻兘鎻忚堪:IC POT DGTL 10K 256POS 10MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯欐簴鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯欐簴鍊� 300 ppm/°C 瀛樺劜鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR)
AD5200BRMZ50 鍔熻兘鎻忚堪:IC POT DGTL 50K 256POS 10MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯欐簴鍖呰:3,300 绯诲垪:WiperLock™ 鎺ョ墖:257 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯欐簴鍊� 150 ppm/°C 瀛樺劜鍣ㄩ鍨�:鏄撳け 鎺ュ彛:3 绶� SPI锛堣姱鐗囬伕鎿囷級 闆绘簮闆诲:1.8 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-VDFN 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:8-DFN-EP锛�3x3锛� 鍖呰:甯跺嵎 (TR)
AD5200BRMZ50-REEL7 鍔熻兘鎻忚堪:IC POT DGTL 50K 256POS 10MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯欐簴鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯欐簴鍊� 300 ppm/°C 瀛樺劜鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR)
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