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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD5200BRMZ10 |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 11/15闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC POT DGTL 10K 256POS 10MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 鎺ョ墖锛� | 256 |
| 闆婚樆锛堟瓙濮嗭級锛� | 10k |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� 500 ppm/°C |
| 瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 鏄撳け |
| 鎺ュ彛锛� | 3 绶氫覆琛岋紙鑺墖閬告搰锛� |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V锛�±2.3 V ~ 2.7 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 10-MSOP |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 786 (CN2011-ZH PDF) |
AD5200/AD5201
鈥�5鈥�
ABSOLUTE MAXIMUM RATINGS
1
(TA = 25
掳C, unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥�0.3, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 鈥�7 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
IMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
卤20 mA2
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . 鈥�40
掳C to +85掳C
Maximum Junction Temperature (TJ Max) . . . . . . . . . 150
掳C
Storage Temperature . . . . . . . . . . . . . . . . . . 鈥�65
掳C to +150掳C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300
掳C
Thermal Resistance
胃
JA,
. . . . . . . . . . . . . 200
掳C/W
Package Power Dissipation = (TJ Max 鈥� TA)/
胃JA
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Max current is bounded by the maximum current handling of the switches,
maximum power dissipation of the package, and maximum applied voltage across
any two of the A, B, and W terminals at a given resistance. Please refer to TPC 31
and TPC 32 for detail.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
10
9
8
7
6
1
2
3
4
5
AD5200/
AD5201
B
VSS
GND
CS
SDI
A
W
VDD
SHDN
CLK
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5200/AD5201 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
Pin
Name
Description
1
B
B Terminal.
2VSS
Negative Power Supply, specified for opera-
tion from 0 V to 鈥�2.7 V.
3
GND
Ground.
4
CS
Chip Select Input, Active Low. When
CS
returns high, data will be loaded into the
DAC register.
5
SDI
Serial Data Input.
6
CLK
Serial Clock Input, positive edge triggered.
7
SHDN
Active Low Input. Terminal A open circuit.
Shutdown controls Variable Resistors of
RDAC to temporary infinite.
8VDD
Positive Power Supply (Sum of VDD + VSS
鈮� 5.5 V).
9
W
Wiper Terminal.
10
A
A Terminal.
MSOP
REV. D
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