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參數(shù)資料
| 型號(hào)： | AD5174BRMZ-10 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 1024POS 10K 10MSOP |
| 產(chǎn)品變化通告： | AD5174 Pin Requirement 14/Dec/2010 |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 接片： | 1024 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | 4 線串行 |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
AD5174
Rev. B | Page 17 of 20
EXT_CAP CAPACITOR
A 1 μF capacitor to VSS must be connected to the EXT_CAP
pin, as shown in Figure 28, on power-up and throughout the
operation of the AD5174.
AD5174
50-TP
MEMORY
BLOCK
EXT_CAP
C1
1F
VSS
08
718
-00
8
Figure 28. EXT_CAP Hardware Setup
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the AD5174
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal A and
Terminal W that exceed VDD or VSS are clamped by the internal
forward-biased diodes (see Figure 29).
VSS
VDD
A
W
08
718
-00
9
Figure 29. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5174 is primarily used as a digital
ground reference. To minimize the digital ground bounce, join the
AD5174 ground terminal remotely to the common ground. The
digital input control signals to the AD5174 must be referenced
to the device ground pin (GND) and must satisfy the logic level
defined in the Specifications section. An internal level shift
circuit ensures that the common-mode voltage range of the
three terminals extends from VSS to VDD, regardless of the
digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A and Terminal W (see Figure 29), it is important to
power VDD/VSS first before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that VDD/VSS are powered unintentionally. The ideal power-
up sequence is VSS, GND, VDD, digital inputs, VA, and VW.
The order of powering VA, VW, and the digital inputs is not
important as long as they are powered after VDD/VSS.
As soon as VDD is powered, the power-on preset activates,
which first sets the RDAC to midscale and then restores the
last programmed 50-TP value to the RDAC register.
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| AD5175 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Channel, 1024-Position, Digital Rheostat with I2C Interface and 50-TP Memory |
| AD5175BCPZ-10-R2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Channel, 1024-Position, Digital Rheostat with I2C Interface and 50-TP Memory |
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